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authorIngo Molnar <mingo@elte.hu>2008-10-12 12:49:27 +0200
committerIngo Molnar <mingo@elte.hu>2008-10-12 12:49:27 +0200
commit1389ac4b976abdc0555280dfc1aa2c3abcc19641 (patch)
tree1ec51aa0b1e33201f6f4f3bebc657f9ec65f8539 /arch/mips/include/asm/cachectl.h
parent69e13ad56f9e2cd81c4f8bfd6267211c10c14c08 (diff)
parentfd048088306656824958e7783ffcee27e241b361 (diff)
Merge branch 'linus' into x86/signal
Conflicts: arch/x86/kernel/signal_64.c
Diffstat (limited to 'arch/mips/include/asm/cachectl.h')
-rw-r--r--arch/mips/include/asm/cachectl.h26
1 files changed, 26 insertions, 0 deletions
diff --git a/arch/mips/include/asm/cachectl.h b/arch/mips/include/asm/cachectl.h
new file mode 100644
index 00000000000..f3ce721861d
--- /dev/null
+++ b/arch/mips/include/asm/cachectl.h
@@ -0,0 +1,26 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994, 1995, 1996 by Ralf Baechle
+ */
+#ifndef _ASM_CACHECTL
+#define _ASM_CACHECTL
+
+/*
+ * Options for cacheflush system call
+ */
+#define ICACHE (1<<0) /* flush instruction cache */
+#define DCACHE (1<<1) /* writeback and flush data cache */
+#define BCACHE (ICACHE|DCACHE) /* flush both caches */
+
+/*
+ * Caching modes for the cachectl(2) call
+ *
+ * cachectl(2) is currently not supported and returns ENOSYS.
+ */
+#define CACHEABLE 0 /* make pages cacheable */
+#define UNCACHEABLE 1 /* make pages uncacheable */
+
+#endif /* _ASM_CACHECTL */