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| author | Linus Torvalds <torvalds@linux-foundation.org> | 2009-05-14 19:19:43 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2009-05-14 19:19:43 -0700 |
| commit | c48f2295a96d12c1c57d4655890af9984d3c061c (patch) | |
| tree | 9d7e96fd4307a896763b4658f33640423f3d244c /arch/mips/include/asm/hazards.h | |
| parent | 5732c468495effd3089c1c893f3eba9a8a1d373c (diff) | |
| parent | 5d81b83d03eb32085c569854695e102dde7af544 (diff) | |
Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (38 commits)
MIPS: Sibyte: Fix locking in set_irq_affinity
MIPS: Use force_sig when handling address errors.
MIPS: Cavium: Add struct clocksource * argument to octeon_cvmcount_read()
MIPS: Rewrite <asm/div64.h> to work with gcc 4.4.0.
MIPS: Fix highmem.
MIPS: Fix sign-extension bug in 32-bit kernel on 32-bit hardware.
MIPS: MSP71xx: Remove the RAMROOT functions
MIPS: Use -mno-check-zero-division
MIPS: Set compiler options only after the compiler prefix has ben set.
MIPS: IP27: Get rid of #ident. Gcc 4.4.0 doesn't like it.
MIPS: uaccess: Switch lock annotations to might_fault().
MIPS: MSP71xx: Resolve use of non-existent GPIO routines in msp71xx reset
MIPS: MSP71xx: Resolve multiple definition of plat_timer_setup
MIPS: Make uaccess.h slightly more sparse friendly.
MIPS: Make access_ok() sideeffect proof.
MIPS: IP27: Fix clash with NMI_OFFSET from hardirq.h
MIPS: Alchemy: Timer build fix
MIPS: Kconfig: Delete duplicate definition of RWSEM_GENERIC_SPINLOCK.
MIPS: Cavium: Add support for 8k and 32k page sizes.
MIPS: TXx9: Fix possible overflow in clock calculations
...
Diffstat (limited to 'arch/mips/include/asm/hazards.h')
| -rw-r--r-- | arch/mips/include/asm/hazards.h | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/arch/mips/include/asm/hazards.h b/arch/mips/include/asm/hazards.h index a12d971db4f..0eaf77ffbc4 100644 --- a/arch/mips/include/asm/hazards.h +++ b/arch/mips/include/asm/hazards.h @@ -138,8 +138,9 @@ do { \ __instruction_hazard(); \ } while (0) -#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \ - defined(CONFIG_CPU_R5500) || defined(CONFIG_MACH_ALCHEMY) +#elif defined(CONFIG_MACH_ALCHEMY) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \ + defined(CONFIG_CPU_LOONGSON2) || defined(CONFIG_CPU_R10000) || \ + defined(CONFIG_CPU_R5500) /* * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer. |