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author | Frederik Deweerdt <frederik.deweerdt@xprog.eu> | 2009-01-12 22:35:42 +0100 |
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committer | Ingo Molnar <mingo@elte.hu> | 2009-01-14 12:04:53 +0100 |
commit | 09b3ec7315a18d885127544204f1e389d41058d0 (patch) | |
tree | a87dbf01992ac7bc5c5f832635e5ecbe95e04e39 /arch/mips/include/asm/mach-ip22 | |
parent | c59765042f53a79a7a65585042ff463b69cb248c (diff) |
x86, tlb flush_data: replace per_cpu with an array
Impact: micro-optimization, memory reduction
On x86_64 flush tlb data is stored in per_cpu variables. This is
unnecessary because only the first NUM_INVALIDATE_TLB_VECTORS entries
are accessed.
This patch aims at making the code less confusing (there's nothing
really "per_cpu") by using a plain array. It also would save some memory
on most distros out there (Ubuntu x86_64 has NR_CPUS=64 by default).
[ Ravikiran G Thirumalai also pointed out that the correct alignment
is ____cacheline_internodealigned_in_smp, so that there's no
bouncing on vsmp. ]
Signed-off-by: Frederik Deweerdt <frederik.deweerdt@xprog.eu>
Acked-by: Ravikiran Thirumalai <kiran@scalex86.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/mips/include/asm/mach-ip22')
0 files changed, 0 insertions, 0 deletions