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authorShinya Kuribayashi <shinya.kuribayashi@necel.com>2009-03-03 18:05:51 +0900
committerRalf Baechle <ralf@linux-mips.org>2009-03-11 21:11:07 +0100
commita644b2774d41409519bb33a16bd577cb41bb3095 (patch)
treea0a8a574ac53e318dbf72306d6b752224ebdbc64 /arch/mips/include/asm/prefetch.h
parentc189846ecf900cd6b3ad7d3cef5b45a746ce646b (diff)
MIPS: NEC VR5500 processor support fixup
Current VR5500 processor support lacks of some functions which are expected to be configured/synthesized on arch initialization. Here're some VR5500A spec notes: * All execution hazards are handled in hardware. * Once VR5500A stops the operation of the pipeline by WAIT instruction, it could return from the standby mode only when either a reset, NMI request, or all enabled interrupts is/are detected. In other words, if interrupts are disabled by Status.IE=0, it keeps in standby mode even when interrupts are internally asserted. Notes on WAIT: The operation of the processor is undefined if WAIT insn is in the branch delay slot. The operation is also undefined if WAIT insn is executed when Status.EXL and Status.ERL are set to 1. * VR5500A core only implements the Load prefetch. With these changes, it boots fine. Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include/asm/prefetch.h')
-rw-r--r--arch/mips/include/asm/prefetch.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/include/asm/prefetch.h b/arch/mips/include/asm/prefetch.h
index 17850834ccb..a56594f360e 100644
--- a/arch/mips/include/asm/prefetch.h
+++ b/arch/mips/include/asm/prefetch.h
@@ -26,7 +26,7 @@
* Pref_WriteBackInvalidate is a nop and Pref_PrepareForStore is broken in
* current versions due to erratum G105.
*
- * VR7701 only implements the Load prefetch.
+ * VR5500 (including VR5701 and VR7701) only implement load prefetch.
*
* Finally MIPS32 and MIPS64 implement all of the following hints.
*/