diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2009-09-17 20:52:32 -0700 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2009-09-17 20:52:32 -0700 |
commit | 3dc95666df0e1ae5b7381a8ec97a583bb3ce4306 (patch) | |
tree | fc1b277f507c48b8c29536947e1de5c2eeda9325 /arch/mips/kernel/cpu-probe.c | |
parent | b938fb6f491113880ebaabfa06c6446723c702fd (diff) | |
parent | 9b1fc55a05006523bced65f4d99f7072831ff56a (diff) |
Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (51 commits)
MIPS: BCM63xx: Add integrated ethernet mac support.
MIPS: BCM63xx: Add support for the Broadcom BCM63xx family of SOCs.
MIPS: BCM63xx: Add Broadcom 63xx CPU definitions.
MIPS: Octeon: Move some platform device registration to its own file.
MIPS: Don't corrupt page tables on vmalloc fault.
MIPS: Shrink the size of tlb handler
MIPS: Alchemy: override loops_per_jiffy detection
MIPS: hw_random: Add hardware RNG for Octeon SOCs.
MIPS: Octeon: Add hardware RNG platform device.
MIPS: Remove useless zero initializations.
MIPS: Alchemy: get rid of allow_au1k_wait
MIPS: Octeon: Set kernel_uses_llsc to false on non-SMP builds.
MIPS: Allow kernel use of LL/SC to be separate from the presence of LL/SC.
MIPS: Get rid of CONFIG_CPU_HAS_LLSC
MIPS: Malta: Remove pointless use use of CONFIG_CPU_HAS_LLSC
MIPS: Rewrite clearing of ll_bit on context switch in C
MIPS: Rewrite sysmips(MIPS_ATOMIC_SET, ...) in C with inline assembler
MIPS: Consolidate all CONFIG_CPU_HAS_LLSC use in a single C file.
MIPS: Clean up linker script using new linker script macros.
MIPS: Use PAGE_SIZE in assembly instead of _PAGE_SIZE.
...
Diffstat (limited to 'arch/mips/kernel/cpu-probe.c')
-rw-r--r-- | arch/mips/kernel/cpu-probe.c | 40 |
1 files changed, 30 insertions, 10 deletions
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 1abe9905c9c..f709657e4dc 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -31,7 +31,7 @@ * The wait instruction stops the pipeline and reduces the power consumption of * the CPU very much. */ -void (*cpu_wait)(void) = NULL; +void (*cpu_wait)(void); static void r3081_wait(void) { @@ -91,16 +91,13 @@ static void rm7k_wait_irqoff(void) local_irq_enable(); } -/* The Au1xxx wait is available only if using 32khz counter or - * external timer source, but specifically not CP0 Counter. */ -int allow_au1k_wait; - +/* + * The Au1xxx wait is available only if using 32khz counter or + * external timer source, but specifically not CP0 Counter. + * alchemy/common/time.c may override cpu_wait! + */ static void au1k_wait(void) { - if (!allow_au1k_wait) - return; - - /* using the wait instruction makes CP0 counter unusable */ __asm__(" .set mips3 \n" " cache 0x14, 0(%0) \n" " cache 0x14, 32(%0) \n" @@ -115,7 +112,7 @@ static void au1k_wait(void) : : "r" (au1k_wait)); } -static int __initdata nowait = 0; +static int __initdata nowait; static int __init wait_disable(char *s) { @@ -159,6 +156,9 @@ void __init check_wait(void) case CPU_25KF: case CPU_PR4450: case CPU_BCM3302: + case CPU_BCM6338: + case CPU_BCM6348: + case CPU_BCM6358: case CPU_CAVIUM_OCTEON: cpu_wait = r4k_wait; break; @@ -857,6 +857,7 @@ static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu) decode_configs(c); switch (c->processor_id & 0xff00) { case PRID_IMP_BCM3302: + /* same as PRID_IMP_BCM6338 */ c->cputype = CPU_BCM3302; __cpu_name[cpu] = "Broadcom BCM3302"; break; @@ -864,6 +865,25 @@ static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu) c->cputype = CPU_BCM4710; __cpu_name[cpu] = "Broadcom BCM4710"; break; + case PRID_IMP_BCM6345: + c->cputype = CPU_BCM6345; + __cpu_name[cpu] = "Broadcom BCM6345"; + break; + case PRID_IMP_BCM6348: + c->cputype = CPU_BCM6348; + __cpu_name[cpu] = "Broadcom BCM6348"; + break; + case PRID_IMP_BCM4350: + switch (c->processor_id & 0xf0) { + case PRID_REV_BCM6358: + c->cputype = CPU_BCM6358; + __cpu_name[cpu] = "Broadcom BCM6358"; + break; + default: + c->cputype = CPU_UNKNOWN; + break; + } + break; } } |