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authorSuresh Siddha <suresh.b.siddha@intel.com>2008-12-18 18:09:21 -0800
committerIngo Molnar <mingo@elte.hu>2008-12-19 09:13:50 +0100
commit345077cd98ff5532b2d1158013c3fec7b1ae85ec (patch)
treeb26a683fca5fcb39f5646219fceecb5a168eec77 /arch/mips/kernel/irq-msc01.c
parent40fb17152c50a69dc304dd632131c2f41281ce44 (diff)
x86: fix intel x86_64 llc_shared_map/cpu_llc_id anomolies
Impact: fix wrong cache sharing detection on platforms supporting > 8 bit apicid's In the presence of extended topology eumeration leaf 0xb provided by cpuid, 32bit extended initial_apicid in cpuinfo_x86 struct will be updated by detect_extended_topology(). At this instance, we should also reinit the apicid (which could also potentially be extended to 32bit). With out this there will potentially be duplicate apicid's populated in the per cpu's cpuinfo_x86 struct, resulting in wrong cache sharing topology etc detected by init_intel_cacheinfo(). Reported-by: Dimitri Sivanich <sivanich@sgi.com> Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com> Acked-by: Dimitri Sivanich <sivanich@sgi.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Cc: <stable@kernel.org>
Diffstat (limited to 'arch/mips/kernel/irq-msc01.c')
0 files changed, 0 insertions, 0 deletions