aboutsummaryrefslogtreecommitdiff
path: root/arch/mips/kernel/traps.c
diff options
context:
space:
mode:
authorRalf Baechle <ralf@linux-mips.org>2007-10-11 23:46:05 +0100
committerRalf Baechle <ralf@linux-mips.org>2007-10-11 23:46:05 +0100
commit641e97f318870921d048154af6807e46e43c307a (patch)
tree6e0984a1bc8932db848be3fdb104a92c97fe341a /arch/mips/kernel/traps.c
parent424b28ba4d25fc41abdb7e6fa90e132f0d9558fb (diff)
[MIPS] Sibyte: Replace SB1 cachecode with standard R4000 class cache code.
It may not be perfect yet but the SB1 code is badly borken and has horrible performance issues. Downside: This seriously breaks support for pass 1 parts of the BCM1250 where indexed cacheops don't work quite reliable but I seem to be the last one on the planet with a pass 1 part anyway. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/kernel/traps.c')
-rw-r--r--arch/mips/kernel/traps.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 3d033e1cd4f..d96f8218a91 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -1435,6 +1435,9 @@ void __init set_handler (unsigned long offset, void *addr, unsigned long size)
flush_icache_range(ebase + offset, ebase + offset + size);
}
+static char panic_null_cerr[] __initdata =
+ "Trying to set NULL cache error exception handler";
+
/* Install uncached CPU exception handler */
void __init set_uncached_handler (unsigned long offset, void *addr, unsigned long size)
{
@@ -1445,6 +1448,9 @@ void __init set_uncached_handler (unsigned long offset, void *addr, unsigned lon
unsigned long uncached_ebase = TO_UNCAC(ebase);
#endif
+ if (!addr)
+ panic(panic_null_cerr);
+
memcpy((void *)(uncached_ebase + offset), addr, size);
}