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authorAndrew Isaacson <adi@broadcom.com>2005-10-19 23:57:40 -0700
committerRalf Baechle <ralf@linux-mips.org>2005-10-29 19:32:48 +0100
commita4b5bd9abcf5b0586de68722ff8e9b91020279bf (patch)
treefe0f4014bf5e92d72d4e15d90cf3eab3713ceee5 /arch/mips/mm/cex-sb1.S
parent9a6dcea10308df50ed54d6d5a43c9f6c3e927118 (diff)
SB1 cache exception handling.
Expand SB1 cache error handling by adding SB1_CEX_ALWAYS_FATAL and SB1_CEX_STALL, allowing configurable behavior on cache errors. Signed-Off-By: Andy Isaacson <adi@broadcom.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/mm/cex-sb1.S')
-rw-r--r--arch/mips/mm/cex-sb1.S5
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/mips/mm/cex-sb1.S b/arch/mips/mm/cex-sb1.S
index 2c3a23aa88c..0e71580774f 100644
--- a/arch/mips/mm/cex-sb1.S
+++ b/arch/mips/mm/cex-sb1.S
@@ -64,6 +64,10 @@ LEAF(except_vec2_sb1)
sd k0,0x170($0)
sd k1,0x178($0)
+#if CONFIG_SB1_CEX_ALWAYS_FATAL
+ j handle_vec2_sb1
+ nop
+#else
/*
* M_ERRCTL_RECOVERABLE is bit 31, which makes it easy to tell
* if we can fast-path out of here for a h/w-recovered error.
@@ -134,6 +138,7 @@ unrecoverable:
/* Unrecoverable Icache or Dcache error; log it and/or fail */
j handle_vec2_sb1
nop
+#endif
END(except_vec2_sb1)