[MIPS] Rewrite all the assembler interrupt handlers to C.

Saves like 1,600 lines of code, is way easier to debug, compilers
frequently do a better job than the cut and paste type of handlers many
boards had.  And finally having all the stuff done in a single place
also means alot of bug potencial for the MT ASE is gone.

The only surviving handler in assembler is the DECstation one; I hope
Maciej will rewrite it.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

3 files changed, 34 insertions, 145 deletions

diff --git a/arch/mips/momentum/ocelot_3/Makefile b/arch/mips/momentum/ocelot_3/Makefile
index aab8fd89f83..8bcea64dd27 100644
--- a/arch/mips/momentum/ocelot_3/Makefile
+++ b/arch/mips/momentum/ocelot_3/Makefile
@@ -5,4 +5,4 @@
 # removes any old dependencies. DON'T put your own dependencies here
 # unless it's something special (ie not a .c file).
 #
-obj-y	 += int-handler.o irq.o prom.o reset.o setup.o
+obj-y	 += irq.o prom.o reset.o setup.o
diff --git a/arch/mips/momentum/ocelot_3/int-handler.S b/arch/mips/momentum/ocelot_3/int-handler.S
deleted file mode 100644
index b1207262984..00000000000
--- a/arch/mips/momentum/ocelot_3/int-handler.S
+++ /dev/null
@@ -1,139 +0,0 @@
-/*
- * Copyright 2002 Momentum Computer Inc.
- * Author: Matthew Dharm <mdharm@momenco.com>
- *
- * Copyright 2001 MontaVista Software Inc.
- * Author: jsun@mvista.com or jsun@junsun.net
- *
- * Copyright 2004 PMC-Sierra
- * Author: Manish Lachwani (lachwani@pmc-sierra.com)
- *
- * Copyright (C) 2004 MontaVista Software Inc.
- * Author: Manish Lachwani, mlachwani@mvista.com
- *
- * First-level interrupt dispatcher for Ocelot-3 board.
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- */
-#include <asm/asm.h>
-#include <asm/mipsregs.h>
-#include <asm/addrspace.h>
-#include <asm/regdef.h>
-#include <asm/stackframe.h>
-
-/*
- * First level interrupt dispatcher for Ocelot-3 board
- */
-		.align	5
-		NESTED(ocelot3_handle_int, PT_SIZE, sp)
-		SAVE_ALL
-		CLI
-		.set	at
-
-		mfc0	t0, CP0_CAUSE
-		mfc0	t2, CP0_STATUS
-
-		and	t0, t2
-
-		andi	t1, t0, STATUSF_IP0	/* sw0 software interrupt (IRQ0) */
-		bnez	t1, ll_sw0_irq
-
-		andi	t1, t0, STATUSF_IP1	/* sw1 software interrupt (IRQ1) */
-		bnez	t1, ll_sw1_irq
-
-		andi	t1, t0, STATUSF_IP2	/* int0 hardware line (IRQ2) */
-		bnez	t1, ll_pci0slot1_irq
-
-		andi	t1, t0, STATUSF_IP3	/* int1 hardware line (IRQ3) */
-		bnez	t1, ll_pci0slot2_irq
-
-		andi	t1, t0, STATUSF_IP4	/* int2 hardware line (IRQ4) */
-		bnez	t1, ll_pci1slot1_irq
-
-		andi	t1, t0, STATUSF_IP5	/* int3 hardware line (IRQ5) */
-		bnez	t1, ll_pci1slot2_irq
-
-		andi	t1, t0, STATUSF_IP6	/* int4 hardware line (IRQ6) */
-		bnez	t1, ll_uart_irq
-
-		andi	t1, t0, STATUSF_IP7	/* cpu timer (IRQ7) */
-		bnez	t1, ll_cputimer_irq
-
-                /* now look at extended interrupts */
-                mfc0    t0, CP0_CAUSE
-                cfc0    t1, CP0_S1_INTCONTROL
-
-                /* shift the mask 8 bits left to line up the bits */
-                sll     t2, t1, 8
-
-                and     t0, t2
-                srl     t0, t0, 16
-
-                andi    t1, t0, STATUSF_IP8     /* int6 hardware line (IRQ9) */
-                bnez    t1, ll_mv64340_decode_irq
-
-		.set	reorder
-
-		/* wrong alarm or masked ... */
-		jal	spurious_interrupt
-		nop
-		j	ret_from_irq
-		 nop
-		END(ocelot3_handle_int)
-
-		.align	5
-ll_sw0_irq:
-		li	a0, 0		/* IRQ 1 */
-		move	a1, sp
-		jal	do_IRQ
-		j	ret_from_irq
-ll_sw1_irq:
-		li	a0, 1		/* IRQ 2 */
-		move	a1, sp
-		jal	do_IRQ
-		j	ret_from_irq
-
-ll_pci0slot1_irq:
-		li	a0, 2		/* IRQ 3 */
-		move	a1, sp
-		jal	do_IRQ
-		j	ret_from_irq
-
-ll_pci0slot2_irq:
-		li	a0, 3		/* IRQ 4 */
-		move	a1, sp
-		jal	do_IRQ
-		j	ret_from_irq
-
-ll_pci1slot1_irq:
-		li	a0, 4		/* IRQ 5 */
-		move	a1, sp
-		jal	do_IRQ
-		j	ret_from_irq
-
-ll_pci1slot2_irq:
-		li	a0, 5		/* IRQ 6 */
-		move	a1, sp
-		jal	do_IRQ
-		j	ret_from_irq
-
-ll_uart_irq:
-		li	a0, 6		/* IRQ 7 */
-		move	a1, sp
-		jal	do_IRQ
-		j	ret_from_irq
-
-ll_cputimer_irq:
-		li	a0, 7		/* IRQ 8 */
-		move	a1, sp
-		jal	do_IRQ
-		j	ret_from_irq
-
-ll_mv64340_decode_irq:
-		move	a0, sp
-		jal	ll_mv64340_irq
-		j	ret_from_irq
-
diff --git a/arch/mips/momentum/ocelot_3/irq.c b/arch/mips/momentum/ocelot_3/irq.c
index 42464dbd4ad..87c63c340ae 100644
--- a/arch/mips/momentum/ocelot_3/irq.c
+++ b/arch/mips/momentum/ocelot_3/irq.c
@@ -53,8 +53,6 @@
 #include <asm/mipsregs.h>
 #include <asm/system.h>
 
-extern asmlinkage void ocelot3_handle_int(void);
-
 static struct irqaction cascade_mv64340 = {
 	no_action, SA_INTERRUPT, CPU_MASK_NONE, "MV64340-Cascade", NULL, NULL
 };
@@ -67,9 +65,6 @@ void __init arch_init_irq(void)
 	 */
 	clear_c0_status(ST0_IM | ST0_BEV);
 
-	/* Sets the first-level interrupt dispatcher. */
-	set_except_vector(0, ocelot3_handle_int);
-	mips_cpu_irq_init(0);
 	rm7k_cpu_irq_init(8);
 
 	/* set up the cascading interrupts */
@@ -79,3 +74,36 @@ void __init arch_init_irq(void)
 	set_c0_status(ST0_IM); /* IE in the status register */
 
 }
+
+asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
+{
+	unsigned int pending = read_c0_cause() & read_c0_status();
+
+	if (pending & STATUSF_IP0)
+		do_IRQ(0, regs);
+	else if (pending & STATUSF_IP1)
+		do_IRQ(1, regs);
+	else if (pending & STATUSF_IP2)
+		do_IRQ(2, regs);
+	else if (pending & STATUSF_IP3)
+		do_IRQ(3, regs);
+	else if (pending & STATUSF_IP4)
+		do_IRQ(4, regs);
+	else if (pending & STATUSF_IP5)
+		do_IRQ(5, regs);
+	else if (pending & STATUSF_IP6)
+		do_IRQ(6, regs);
+	else if (pending & STATUSF_IP7)
+		do_IRQ(7, regs);
+	else {
+		/*
+		 * Now look at the extended interrupts
+		 */
+		pending = (read_c0_cause() & (read_c0_intcontrol() << 8)) >> 16;
+
+		if (pending & STATUSF_IP8)
+			ll_mv64340_irq(regs);
+		else
+			spurious_interrupt(regs);
+	}
+}