diff options
| author | Ingo Molnar <mingo@elte.hu> | 2009-09-02 08:17:56 +0200 |
|---|---|---|
| committer | Ingo Molnar <mingo@elte.hu> | 2009-09-02 08:17:56 +0200 |
| commit | 936e894a976dd3b0f07f1f6f43c17b77b7e6146d (patch) | |
| tree | 5ed5c1f6735dcd26550594df23c8f7fe2aa21a15 /arch/mips/pmc-sierra | |
| parent | 69575d388603365f2afbf4166df93152df59b165 (diff) | |
| parent | 326ba5010a5429a5a528b268b36a5900d4ab0eba (diff) | |
Merge commit 'v2.6.31-rc8' into x86/txt
Conflicts:
arch/x86/kernel/reboot.c
security/Kconfig
Merge reason: resolve the conflicts, bump up from rc3 to rc8.
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/mips/pmc-sierra')
| -rw-r--r-- | arch/mips/pmc-sierra/msp71xx/gpio.c | 2 | ||||
| -rw-r--r-- | arch/mips/pmc-sierra/msp71xx/gpio_extended.c | 2 | ||||
| -rw-r--r-- | arch/mips/pmc-sierra/msp71xx/msp_irq_slp.c | 12 | ||||
| -rw-r--r-- | arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.c | 2 |
4 files changed, 2 insertions, 16 deletions
diff --git a/arch/mips/pmc-sierra/msp71xx/gpio.c b/arch/mips/pmc-sierra/msp71xx/gpio.c index 69848c5813e..aaccbe52438 100644 --- a/arch/mips/pmc-sierra/msp71xx/gpio.c +++ b/arch/mips/pmc-sierra/msp71xx/gpio.c @@ -1,6 +1,4 @@ /* - * @file /arch/mips/pmc-sierra/msp71xx/gpio.c - * * Generic PMC MSP71xx GPIO handling. These base gpio are controlled by two * types of registers. The data register sets the output level when in output * mode and when in input mode will contain the value at the input. The config diff --git a/arch/mips/pmc-sierra/msp71xx/gpio_extended.c b/arch/mips/pmc-sierra/msp71xx/gpio_extended.c index fc6dbc6cf1c..2a99f360fae 100644 --- a/arch/mips/pmc-sierra/msp71xx/gpio_extended.c +++ b/arch/mips/pmc-sierra/msp71xx/gpio_extended.c @@ -1,6 +1,4 @@ /* - * @file /arch/mips/pmc-sierra/msp71xx/gpio_extended.c - * * Generic PMC MSP71xx EXTENDED (EXD) GPIO handling. The extended gpio is * a set of hardware registers that have no need for explicit locking as * it is handled by unique method of writing individual set/clr bits. diff --git a/arch/mips/pmc-sierra/msp71xx/msp_irq_slp.c b/arch/mips/pmc-sierra/msp71xx/msp_irq_slp.c index f5f1b8d2bb9..61f39023234 100644 --- a/arch/mips/pmc-sierra/msp71xx/msp_irq_slp.c +++ b/arch/mips/pmc-sierra/msp71xx/msp_irq_slp.c @@ -45,13 +45,6 @@ static inline void mask_msp_slp_irq(unsigned int irq) */ static inline void ack_msp_slp_irq(unsigned int irq) { - mask_slp_irq(irq); - - /* - * only really necessary for 18, 16-14 and sometimes 3:0 (since - * these can be edge sensitive) but it doesn't hurt for the others. - */ - /* check for PER interrupt range */ if (irq < MSP_PER_INTBASE) *SLP_INT_STS_REG = (1 << (irq - MSP_SLP_INTBASE)); @@ -62,8 +55,7 @@ static inline void ack_msp_slp_irq(unsigned int irq) static struct irq_chip msp_slp_irq_controller = { .name = "MSP_SLP", .ack = ack_msp_slp_irq, - .mask = ack_msp_slp_irq, - .mask_ack = ack_msp_slp_irq, + .mask = mask_msp_slp_irq, .unmask = unmask_msp_slp_irq, }; @@ -79,7 +71,7 @@ void __init msp_slp_irq_init(void) /* initialize all the IRQ descriptors */ for (i = MSP_SLP_INTBASE; i < MSP_PER_INTBASE + 32; i++) - set_irq_chip_and_handler(i, &msp_slp_irq_controller + set_irq_chip_and_handler(i, &msp_slp_irq_controller, handle_level_irq); } diff --git a/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.c b/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.c index caf5e9a0acc..fc990cb3194 100644 --- a/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.c +++ b/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.c @@ -1,6 +1,4 @@ /* - * arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.c - * * Copyright (C) 2003 PMC-Sierra Inc. * Author: Manish Lachwani (lachwani@pmc-sierra.com) * |