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authorThiemo Seufer <ths@networkno.de>2006-07-05 14:26:38 +0100
committerRalf Baechle <ralf@linux-mips.org>2006-07-13 21:26:05 +0100
commit6e61e85b0980f7b88cd5c4b822386ed00dd7e295 (patch)
tree8541546073f5ea9131f881196519f28fc047ecb8 /arch/mips/sibyte/sb1250/irq.c
parentfc5d2d279ff820172a698706d33e733d4578bd6c (diff)
[MIPS] Sibyte: Improve interrupt latency again for sb1250/bcm1480
this patch restores the behaviour of the old (assembly-written) interrupt handler, the handler is left as soon as a single interrupt cause is handled. Signed-off-by: Thiemo Seufer <ths@networkno.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/sibyte/sb1250/irq.c')
-rw-r--r--arch/mips/sibyte/sb1250/irq.c10
1 files changed, 5 insertions, 5 deletions
diff --git a/arch/mips/sibyte/sb1250/irq.c b/arch/mips/sibyte/sb1250/irq.c
index 8d49cb52d19..1de71adec6c 100644
--- a/arch/mips/sibyte/sb1250/irq.c
+++ b/arch/mips/sibyte/sb1250/irq.c
@@ -460,25 +460,25 @@ asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
pending = read_c0_cause();
#ifdef CONFIG_SIBYTE_SB1250_PROF
- if (pending & CAUSEF_IP7) { /* Cpu performance counter interrupt */
+ if (pending & CAUSEF_IP7) /* Cpu performance counter interrupt */
sbprof_cpu_intr(exception_epc(regs));
- }
+ else
#endif
if (pending & CAUSEF_IP4)
sb1250_timer_interrupt(regs);
#ifdef CONFIG_SMP
- if (pending & CAUSEF_IP3)
+ else if (pending & CAUSEF_IP3)
sb1250_mailbox_interrupt(regs);
#endif
#ifdef CONFIG_KGDB
- if (pending & CAUSEF_IP6) /* KGDB (uart 1) */
+ else if (pending & CAUSEF_IP6) /* KGDB (uart 1) */
sb1250_kgdb_interrupt(regs);
#endif
- if (pending & CAUSEF_IP2) {
+ else if (pending & CAUSEF_IP2) {
unsigned long long mask;
/*