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authorAtsushi Nemoto <anemo@mba.ocn.ne.jp>2008-08-19 22:55:12 +0900
committerRalf Baechle <ralf@linux-mips.org>2008-10-11 16:18:43 +0100
commit74894363499942a76f2c20e41e8bfebc9fdc267a (patch)
tree8fbd3b9ab9827e5aff75236b32818822c1b8a4ce /arch/mips/txx9/generic
parent51f607c76e1e7bd089dcad97b6b0a58649be06a3 (diff)
MIPS: TXx9: Raise priority of interrupts for errors, timers, SIO
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/txx9/generic')
-rw-r--r--arch/mips/txx9/generic/irq_tx4927.c11
-rw-r--r--arch/mips/txx9/generic/irq_tx4938.c11
2 files changed, 22 insertions, 0 deletions
diff --git a/arch/mips/txx9/generic/irq_tx4927.c b/arch/mips/txx9/generic/irq_tx4927.c
index cbea1fdde82..ad2870def8f 100644
--- a/arch/mips/txx9/generic/irq_tx4927.c
+++ b/arch/mips/txx9/generic/irq_tx4927.c
@@ -30,8 +30,19 @@
void __init tx4927_irq_init(void)
{
+ int i;
+
mips_cpu_irq_init();
txx9_irq_init(TX4927_IRC_REG & 0xfffffffffULL);
set_irq_chained_handler(MIPS_CPU_IRQ_BASE + TX4927_IRC_INT,
handle_simple_irq);
+ /* raise priority for errors, timers, SIO */
+ txx9_irq_set_pri(TX4927_IR_ECCERR, 7);
+ txx9_irq_set_pri(TX4927_IR_WTOERR, 7);
+ txx9_irq_set_pri(TX4927_IR_PCIERR, 7);
+ txx9_irq_set_pri(TX4927_IR_PCIPME, 7);
+ for (i = 0; i < TX4927_NUM_IR_TMR; i++)
+ txx9_irq_set_pri(TX4927_IR_TMR(i), 6);
+ for (i = 0; i < TX4927_NUM_IR_SIO; i++)
+ txx9_irq_set_pri(TX4927_IR_SIO(i), 5);
}
diff --git a/arch/mips/txx9/generic/irq_tx4938.c b/arch/mips/txx9/generic/irq_tx4938.c
index 6eac684bf19..025ae11359a 100644
--- a/arch/mips/txx9/generic/irq_tx4938.c
+++ b/arch/mips/txx9/generic/irq_tx4938.c
@@ -18,8 +18,19 @@
void __init tx4938_irq_init(void)
{
+ int i;
+
mips_cpu_irq_init();
txx9_irq_init(TX4938_IRC_REG & 0xfffffffffULL);
set_irq_chained_handler(MIPS_CPU_IRQ_BASE + TX4938_IRC_INT,
handle_simple_irq);
+ /* raise priority for errors, timers, SIO */
+ txx9_irq_set_pri(TX4938_IR_ECCERR, 7);
+ txx9_irq_set_pri(TX4938_IR_WTOERR, 7);
+ txx9_irq_set_pri(TX4938_IR_PCIERR, 7);
+ txx9_irq_set_pri(TX4938_IR_PCIPME, 7);
+ for (i = 0; i < TX4938_NUM_IR_TMR; i++)
+ txx9_irq_set_pri(TX4938_IR_TMR(i), 6);
+ for (i = 0; i < TX4938_NUM_IR_SIO; i++)
+ txx9_irq_set_pri(TX4938_IR_SIO(i), 5);
}