aboutsummaryrefslogtreecommitdiff
path: root/arch/powerpc/boot/dts/mpc8541cds.dts
diff options
context:
space:
mode:
authorKumar Gala <galak@kernel.crashing.org>2008-05-30 13:43:43 -0500
committerKumar Gala <galak@kernel.crashing.org>2008-06-02 14:44:25 -0500
commitc054065bc10a7ee2bcf78b5bc95f4b4d9bdc923a (patch)
tree023b60c1b55c04c2db08983a3aaef151d081fcac /arch/powerpc/boot/dts/mpc8541cds.dts
parentacd4b715ec83e451990bb82bdbf28ecaeab1b67d (diff)
[POWERPC] 85xx: Add next-level-cache property
Added next-level-cache to the L1 and a reference to the new L2 label. This is per the ePAPR 0.94 spec. Since we are't really dependent on this today we aren't supporting the "legacy" l2-cache phandle that is specified in the PPC v2.1 OF Binding spec. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/boot/dts/mpc8541cds.dts')
-rw-r--r--arch/powerpc/boot/dts/mpc8541cds.dts3
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/powerpc/boot/dts/mpc8541cds.dts b/arch/powerpc/boot/dts/mpc8541cds.dts
index 21ebe7cc454..66192aa0f31 100644
--- a/arch/powerpc/boot/dts/mpc8541cds.dts
+++ b/arch/powerpc/boot/dts/mpc8541cds.dts
@@ -40,6 +40,7 @@
timebase-frequency = <0>; // 33 MHz, from uboot
bus-frequency = <0>; // 166 MHz
clock-frequency = <0>; // 825 MHz, from uboot
+ next-level-cache = <&L2>;
};
};
@@ -63,7 +64,7 @@
interrupts = <18 2>;
};
- l2-cache-controller@20000 {
+ L2: l2-cache-controller@20000 {
compatible = "fsl,8541-l2-cache-controller";
reg = <0x20000 0x1000>;
cache-line-size = <32>; // 32 bytes