diff options
| author | Stefan Roese <sr@denx.de> | 2007-12-21 15:39:38 +1100 |
|---|---|---|
| committer | Josh Boyer <jwboyer@linux.vnet.ibm.com> | 2007-12-23 13:19:03 -0600 |
| commit | accf5ef254b9dd4d3b53040dd73d80875c2cd39b (patch) | |
| tree | 93ef10f49c2b5d3b4f8874ea713bac93e0a1eeb8 /arch/powerpc/boot/dts | |
| parent | 25c24f3dc7f01491ea0d92a1de2bb84094b27e21 (diff) | |
[POWERPC] 4xx: Add 440SPe revA runtime detection to PCIe
This patch adds runtime detection of the 440SPe revision A chips. These
chips are equipped with a slighly different PCIe core and need special/
different initialization. The compatible node is changed to
"plb-pciex-440spe" ("A" and "B" dropped). This is needed for boards that
can be equipped with both PPC revisions like the AMCC Yucca.
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
Diffstat (limited to 'arch/powerpc/boot/dts')
| -rw-r--r-- | arch/powerpc/boot/dts/katmai.dts | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/powerpc/boot/dts/katmai.dts b/arch/powerpc/boot/dts/katmai.dts index cc2810e0551..d4dedc2e44c 100644 --- a/arch/powerpc/boot/dts/katmai.dts +++ b/arch/powerpc/boot/dts/katmai.dts @@ -267,7 +267,7 @@ #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; - compatible = "ibm,plb-pciex-440speB", "ibm,plb-pciex"; + compatible = "ibm,plb-pciex-440spe", "ibm,plb-pciex"; primary; port = <0>; /* port number */ reg = <d 00000000 20000000 /* Config space access */ @@ -308,7 +308,7 @@ #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; - compatible = "ibm,plb-pciex-440speB", "ibm,plb-pciex"; + compatible = "ibm,plb-pciex-440spe", "ibm,plb-pciex"; primary; port = <1>; /* port number */ reg = <d 20000000 20000000 /* Config space access */ @@ -349,7 +349,7 @@ #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; - compatible = "ibm,plb-pciex-440speB", "ibm,plb-pciex"; + compatible = "ibm,plb-pciex-440spe", "ibm,plb-pciex"; primary; port = <2>; /* port number */ reg = <d 40000000 20000000 /* Config space access */ |