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| author | Linus Torvalds <torvalds@linux-foundation.org> | 2010-01-18 14:08:55 -0800 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2010-01-18 14:08:55 -0800 |
| commit | 8888be69adea1d86d694096cb206ef570e2d691a (patch) | |
| tree | ba3fd0c0b7d7dd7c8d7b7afeb56f094b65ebdb66 /arch/powerpc/kernel/head_8xx.S | |
| parent | 1e868d8e6d2c4b8736cdf7a4bd5701e4f527f722 (diff) | |
| parent | 78924577f493c6fa62e2b38356faa542fa7583e6 (diff) | |
Merge branch 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc
* 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc:
powerpc: Move cpu hotplug driver lock from pseries to powerpc
powerpc: Move /proc/ppc64 to /proc/powerpc update
powerpc/8xx: Fix user space TLB walk in dcbX fixup
powerpc: Fix decrementer setup on 1GHz boards
powerpc/iseries: Initialise on-stack completion
powerpc/hvc: Driver build breaks with !HVC_CONSOLE
serial/pmac_zilog: Workaround problem due to interrupt on closed port
powerpc/macintosh: Make Open Firmware device id constant
powerpc: Use helpers for rlimits
powerpc: cpumask_of_node() should handle -1 as a node
powerpc/pseries: Fix dlpar compile warning without CONFIG_PROC_DEVICETREE
powerpc/pseries: Fix xics interrupt affinity
powerpc/swsusp_32: Fix TLB invalidation
powerpc/8xx: Always pin kernel instruction TLB
powerpc: 2.6.33 update of defconfigs for embedded 6xx/7xxx, 8xx, 8xxx
powerpc: Use scripts/mkuboot.sh instead of 'mkimage'
powerpc/5200: update defconfigs
Diffstat (limited to 'arch/powerpc/kernel/head_8xx.S')
| -rw-r--r-- | arch/powerpc/kernel/head_8xx.S | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S index 678f98cd5e6..3ef743fa5d7 100644 --- a/arch/powerpc/kernel/head_8xx.S +++ b/arch/powerpc/kernel/head_8xx.S @@ -542,11 +542,11 @@ DARFixed:/* Return from dcbx instruction bug workaround, r10 holds value of DAR FixupDAR:/* Entry point for dcbx workaround. */ /* fetch instruction from memory. */ mfspr r10, SPRN_SRR0 + andis. r11, r10, 0x8000 /* Address >= 0x80000000 */ DO_8xx_CPU6(0x3780, r3) mtspr SPRN_MD_EPN, r10 mfspr r11, SPRN_M_TWB /* Get level 1 table entry address */ - cmplwi cr0, r11, 0x0800 - blt- 3f /* Branch if user space */ + beq- 3f /* Branch if user space */ lis r11, (swapper_pg_dir-PAGE_OFFSET)@h ori r11, r11, (swapper_pg_dir-PAGE_OFFSET)@l rlwimi r11, r10, 32-20, 0xffc /* r11 = r11&~0xffc|(r10>>20)&0xffc */ @@ -768,12 +768,12 @@ start_here: */ initial_mmu: tlbia /* Invalidate all TLB entries */ -#ifdef CONFIG_PIN_TLB +/* Always pin the first 8 MB ITLB to prevent ITLB + misses while mucking around with SRR0/SRR1 in asm +*/ lis r8, MI_RSV4I@h ori r8, r8, 0x1c00 -#else - li r8, 0 -#endif + mtspr SPRN_MI_CTR, r8 /* Set instruction MMU control */ #ifdef CONFIG_PIN_TLB |