diff options
| author | Scott Wood <scottwood@freescale.com> | 2007-06-25 14:50:41 -0500 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2007-10-03 20:36:36 -0500 |
| commit | 7401685242fbcbf4b0660726372c77a88c4af17d (patch) | |
| tree | 71b814468d705c2c48184161c38a0295c832239d /arch/powerpc/kernel | |
| parent | 663edbd2640447dc43840568cd5701e6c9878d63 (diff) | |
[POWERPC] 8xx: Work around CPU15 erratum.
The CPU15 erratum on MPC8xx chips can cause incorrect code execution
under certain circumstances, where there is a conditional or indirect
branch in the last word of a page, with a target in the last cache line
of the next page. This patch implements one of the suggested
workarounds, by forcing a TLB miss whenever execution crosses a page
boundary. This is done by invalidating the pages before and after the
one being loaded into the TLB in the ITLB miss handler.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/kernel')
| -rw-r--r-- | arch/powerpc/kernel/head_8xx.S | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S index 9c30938aad5..f7458396cd7 100644 --- a/arch/powerpc/kernel/head_8xx.S +++ b/arch/powerpc/kernel/head_8xx.S @@ -298,6 +298,12 @@ InstructionTLBMiss: stw r10, 0(r0) stw r11, 4(r0) mfspr r10, SPRN_SRR0 /* Get effective address of fault */ +#ifdef CONFIG_8xx_CPU15 + addi r11, r10, 0x1000 + tlbie r11 + addi r11, r10, -0x1000 + tlbie r11 +#endif DO_8xx_CPU6(0x3780, r3) mtspr SPRN_MD_EPN, r10 /* Have to use MD_EPN for walk, MI_EPN can't */ mfspr r10, SPRN_M_TWB /* Get level 1 table entry address */ |