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authorLiu Dave-r63238 <DaveLiu@freescale.com>2006-10-18 16:36:56 +0800
committerPaul Mackerras <paulus@samba.org>2006-10-25 13:49:22 +1000
commitf84c39da766b4c8f13872282f58286a57ad05b3e (patch)
tree22241d3e48d2d765b7f6c92467956e6d0cb1763d /arch/powerpc
parentb910ecf6bf221bb06f37e44765307c42b20db205 (diff)
[POWERPC] Fix the UCC rx/tx clock of QE
MPC8323EMDS board ethernet interface with RMII uses the CLK16 divisor for the rx and tx clock, but the ucc_set_qe_mux_rxtx() function doesn't handle the CLK16 setting of the CMXUCR3 and CMXUCR4 registers. This fixes it. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'arch/powerpc')
-rw-r--r--arch/powerpc/sysdev/qe_lib/ucc.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/powerpc/sysdev/qe_lib/ucc.c b/arch/powerpc/sysdev/qe_lib/ucc.c
index 916c9e5df57..ac12a44d516 100644
--- a/arch/powerpc/sysdev/qe_lib/ucc.c
+++ b/arch/powerpc/sysdev/qe_lib/ucc.c
@@ -207,6 +207,7 @@ int ucc_set_qe_mux_rxtx(int ucc_num, enum qe_clock clock, enum comm_dir mode)
case QE_CLK18: source = 8; break;
case QE_CLK7: source = 9; break;
case QE_CLK8: source = 10; break;
+ case QE_CLK16: source = 11; break;
default: source = -1; break;
}
break;
@@ -222,6 +223,7 @@ int ucc_set_qe_mux_rxtx(int ucc_num, enum qe_clock clock, enum comm_dir mode)
case QE_CLK22: source = 8; break;
case QE_CLK7: source = 9; break;
case QE_CLK8: source = 10; break;
+ case QE_CLK16: source = 11; break;
default: source = -1; break;
}
break;