diff options
| author | Wolfgang Grandegger <wg@grandegger.com> | 2008-08-17 10:51:25 +0200 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2008-08-20 23:56:30 -0500 |
| commit | d27a736c7a62c3451e389aa8e0dfc64dab119b9b (patch) | |
| tree | 56def6d207e8c9b60d5d17fb5f7248693c0aae0f /arch/powerpc | |
| parent | ba1616d921429ffe7480e8835e85f95ff041add8 (diff) | |
powerpc/85xx: TQM8548: DTS file fixes and cleanup
Due to the missing compatible property for the SOC, the MPC I2C buses are
not found any more. This patch fixes this issue. Furthermore it corrects
the name of the SOC node and adds the missing I2C node for the RTC.
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc')
| -rw-r--r-- | arch/powerpc/boot/dts/tqm8548-bigflash.dts | 8 | ||||
| -rw-r--r-- | arch/powerpc/boot/dts/tqm8548.dts | 3 |
2 files changed, 9 insertions, 2 deletions
diff --git a/arch/powerpc/boot/dts/tqm8548-bigflash.dts b/arch/powerpc/boot/dts/tqm8548-bigflash.dts index 64d2d5bbcdf..4199e89b4e5 100644 --- a/arch/powerpc/boot/dts/tqm8548-bigflash.dts +++ b/arch/powerpc/boot/dts/tqm8548-bigflash.dts @@ -50,13 +50,14 @@ reg = <0x00000000 0x00000000>; // Filled in by U-Boot }; - soc8548@a0000000 { + soc@a0000000 { #address-cells = <1>; #size-cells = <1>; device_type = "soc"; ranges = <0x0 0xa0000000 0x100000>; reg = <0xa0000000 0x1000>; // CCSRBAR bus-frequency = <0>; + compatible = "fsl,mpc8548-immr", "simple-bus"; memory-controller@2000 { compatible = "fsl,mpc8548-memory-controller"; @@ -83,6 +84,11 @@ interrupts = <43 2>; interrupt-parent = <&mpic>; dfsrr; + + rtc@68 { + compatible = "dallas,ds1337"; + reg = <0x68>; + }; }; i2c@3100 { diff --git a/arch/powerpc/boot/dts/tqm8548.dts b/arch/powerpc/boot/dts/tqm8548.dts index 2563112cabd..58ee4185454 100644 --- a/arch/powerpc/boot/dts/tqm8548.dts +++ b/arch/powerpc/boot/dts/tqm8548.dts @@ -50,13 +50,14 @@ reg = <0x00000000 0x00000000>; // Filled in by U-Boot }; - soc8548@e0000000 { + soc@e0000000 { #address-cells = <1>; #size-cells = <1>; device_type = "soc"; ranges = <0x0 0xe0000000 0x100000>; reg = <0xe0000000 0x1000>; // CCSRBAR bus-frequency = <0>; + compatible = "fsl,mpc8548-immr", "simple-bus"; memory-controller@2000 { compatible = "fsl,mpc8548-memory-controller"; |