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authorStephen Rothwell <sfr@canb.auug.org.au>2005-10-17 11:50:32 +1000
committerStephen Rothwell <sfr@canb.auug.org.au>2005-10-17 11:50:32 +1000
commit7dffb72028bfd909ac51a1546d182de2df4d2426 (patch)
treec465c35642872973543f710f8aa06b955b84f7e5 /arch/ppc/syslib
parentcf764855620aa1aa5b134687ca18b841ac9be4c7 (diff)
ppc32: use L1_CACHE_SHIFT/L1_CACHE_BYTES
instead of L1_CACHE_LINE_SIZE and LG_L1_CACHE_LINE_SIZE Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
Diffstat (limited to 'arch/ppc/syslib')
-rw-r--r--arch/ppc/syslib/mv64x60.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/ppc/syslib/mv64x60.c b/arch/ppc/syslib/mv64x60.c
index 4849850a59e..a781c50d2f4 100644
--- a/arch/ppc/syslib/mv64x60.c
+++ b/arch/ppc/syslib/mv64x60.c
@@ -1304,7 +1304,7 @@ mv64x60_config_pci_params(struct pci_controller *hose,
early_write_config_word(hose, 0, devfn, PCI_COMMAND, u16_val);
/* Set latency timer, cache line size, clear BIST */
- u16_val = (pi->latency_timer << 8) | (L1_CACHE_LINE_SIZE >> 2);
+ u16_val = (pi->latency_timer << 8) | (L1_CACHE_BYTES >> 2);
early_write_config_word(hose, 0, devfn, PCI_CACHE_LINE_SIZE, u16_val);
mv64x60_pci_exclude_bridge = save_exclude;