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authorMagnus Damm <damm@igel.co.jp>2009-06-02 09:22:02 +0000
committerPaul Mundt <lethal@linux-sh.org>2009-06-11 09:08:53 +0300
commit0d4fdbb64f472ef31195714993f1263f77cf85ca (patch)
tree2cfa619828ac2430919b3d716635e9ebf6f00a47 /arch/sh/boards
parent2693e2740ddae364a80e6083043ba760b6366b69 (diff)
sh: rework mode pin code
This patch reworks the mode pin code to keep the pin definitions in one place. The mode pins values are now the value of the bit instead of bit number. With this patch in place the sh7785 header file contains mode pin comments. The sh7785 clock code and the sh7785lcr board code are updated to reflect the new shared mode pins. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/boards')
-rw-r--r--arch/sh/boards/board-sh7785lcr.c14
1 files changed, 7 insertions, 7 deletions
diff --git a/arch/sh/boards/board-sh7785lcr.c b/arch/sh/boards/board-sh7785lcr.c
index c2894c5b71e..7be56fb06c1 100644
--- a/arch/sh/boards/board-sh7785lcr.c
+++ b/arch/sh/boards/board-sh7785lcr.c
@@ -330,13 +330,13 @@ static int sh7785lcr_mode_pins(void)
* If you change these dip switches then you will need to
* adjust the values below as well.
*/
- value |= 1 << MODE_PIN_MODE4; /* Clock Mode 16 */
- value |= 1 << MODE_PIN_MODE5; /* 32-bit Area0 bus width */
- value |= 1 << MODE_PIN_MODE6; /* 32-bit Area0 bus width */
- value |= 1 << MODE_PIN_MODE7; /* Area 0 SRAM interface [fixed] */
- value |= 1 << MODE_PIN_MODE8; /* Little Endian */
- value |= 1 << MODE_PIN_MODE9; /* Master Mode */
- value |= 1 << MODE_PIN_MODE14; /* No PLL step-up */
+ value |= MODE_PIN4; /* Clock Mode 16 */
+ value |= MODE_PIN5; /* 32-bit Area0 bus width */
+ value |= MODE_PIN6; /* 32-bit Area0 bus width */
+ value |= MODE_PIN7; /* Area 0 SRAM interface [fixed] */
+ value |= MODE_PIN8; /* Little Endian */
+ value |= MODE_PIN9; /* Master Mode */
+ value |= MODE_PIN14; /* No PLL step-up */
return value;
}