diff options
author | Nobuhiro Iwamatsu <iwamatsu@nigauri.org> | 2007-03-26 14:27:43 +0900 |
---|---|---|
committer | Paul Mundt <lethal@hera.kernel.org> | 2007-05-07 02:10:54 +0000 |
commit | c86c5a910451dd5a30e62a9e36d8e9b3c7a0c1d1 (patch) | |
tree | 69acbb65e61a8895dfdebfd70dc58f5d8d9dbe38 /arch/sh/drivers/pci/ops-lboxre2.c | |
parent | 00e8c494a1603eac0a2cae9836e624a752ad45b1 (diff) |
sh: L-BOX RE2 support.
This adds support for the L-BOX RE2 router.
http://www.nttcom.co.jp/l-box/
L-BOX RE2 is a SH7751R-based router. It has CF, Cardbus, serial,
and LAN x2. This is one of the very few SH boards that a general
person can obtain now.
The L-BOX shipped with a 2.4.28 kernel, this is a rewritten patch
adding it to current git.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/drivers/pci/ops-lboxre2.c')
-rw-r--r-- | arch/sh/drivers/pci/ops-lboxre2.c | 63 |
1 files changed, 63 insertions, 0 deletions
diff --git a/arch/sh/drivers/pci/ops-lboxre2.c b/arch/sh/drivers/pci/ops-lboxre2.c new file mode 100644 index 00000000000..a13cb764b0b --- /dev/null +++ b/arch/sh/drivers/pci/ops-lboxre2.c @@ -0,0 +1,63 @@ +/* + * linux/arch/sh/drivers/pci/ops-lboxre2.c + * + * Copyright (C) 2007 Nobuhiro Iwamatsu + * + * PCI initialization for the NTT COMWARE L-BOX RE2 + */ +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/init.h> +#include <linux/pci.h> +#include <linux/io.h> +#include <asm/lboxre2.h> +#include "pci-sh4.h" + +static char lboxre2_irq_tab[] __initdata = { + IRQ_ETH0, IRQ_ETH1, IRQ_INTA, IRQ_INTD, +}; + +int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin) +{ + return lboxre2_irq_tab[slot]; +} + +static struct resource sh7751_io_resource = { + .name = "SH7751_IO", + .start = SH7751_PCI_IO_BASE , + .end = SH7751_PCI_IO_BASE + SH7751_PCI_IO_SIZE - 1, + .flags = IORESOURCE_IO +}; + +static struct resource sh7751_mem_resource = { + .name = "SH7751_mem", + .start = SH7751_PCI_MEMORY_BASE, + .end = SH7751_PCI_MEMORY_BASE + SH7751_PCI_MEM_SIZE - 1, + .flags = IORESOURCE_MEM +}; + +extern struct pci_ops sh7751_pci_ops; + +struct pci_channel board_pci_channels[] = { + { &sh4_pci_ops, &sh7751_io_resource, &sh7751_mem_resource, 0, 0xff }, + { NULL, NULL, NULL, 0, 0 }, +}; + +EXPORT_SYMBOL(board_pci_channels); + +static struct sh4_pci_address_map sh7751_pci_map = { + .window0 = { + .base = SH7751_CS3_BASE_ADDR, + .size = 0x04000000, + }, + .window1 = { + .base = 0x00000000, /* Unused */ + .size = 0x00000000, /* Unused */ + }, + .flags = SH4_PCIC_NO_RESET, +}; + +int __init pcibios_init_platform(void) +{ + return sh7751_pcic_init(&sh7751_pci_map); +} |