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authorPaul Mundt <lethal@linux-sh.org>2009-08-16 01:50:17 +0900
committerPaul Mundt <lethal@linux-sh.org>2009-08-16 01:50:17 +0900
commit94ecd224c940830e2f2724c3860eb7fb74c15d31 (patch)
treeb3940834bc26796af862acf1a24810a2d0d865c9 /arch/sh/include/asm/system.h
parent1ee4ab09f38b77b3a5750429d456d6606b237924 (diff)
sh: Fix up the SH-5 build with caches enabled.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/include/asm/system.h')
-rw-r--r--arch/sh/include/asm/system.h14
1 files changed, 1 insertions, 13 deletions
diff --git a/arch/sh/include/asm/system.h b/arch/sh/include/asm/system.h
index ab79e1f4fbe..bf7c4cbde37 100644
--- a/arch/sh/include/asm/system.h
+++ b/arch/sh/include/asm/system.h
@@ -14,18 +14,6 @@
#define AT_VECTOR_SIZE_ARCH 5 /* entries in ARCH_DLINFO */
-#if defined(CONFIG_CPU_SH4A) || defined(CONFIG_CPU_SH5)
-#define __icbi() \
-{ \
- unsigned long __addr; \
- __addr = 0xa8000000; \
- __asm__ __volatile__( \
- "icbi %0\n\t" \
- : /* no output */ \
- : "m" (__m(__addr))); \
-}
-#endif
-
/*
* A brief note on ctrl_barrier(), the control register write barrier.
*
@@ -44,7 +32,7 @@
#define mb() __asm__ __volatile__ ("synco": : :"memory")
#define rmb() mb()
#define wmb() __asm__ __volatile__ ("synco": : :"memory")
-#define ctrl_barrier() __icbi()
+#define ctrl_barrier() __icbi(0xa8000000)
#define read_barrier_depends() do { } while(0)
#else
#define mb() __asm__ __volatile__ ("": : :"memory")