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authorJames Bottomley <James.Bottomley@HansenPartnership.com>2009-06-12 10:02:03 -0500
committerJames Bottomley <James.Bottomley@HansenPartnership.com>2009-06-12 10:02:03 -0500
commit82681a318f9f028ea64e61f24bbd9ac535531921 (patch)
tree529b6a5b4fd040fb54b7672b1a224ebd47445876 /arch/sh/include/asm/unaligned-sh4a.h
parent3860c97bd60a4525bb62eb90e3e7d2f02662ac59 (diff)
parent8ebf975608aaebd7feb33d77f07ba21a6380e086 (diff)
[SCSI] Merge branch 'linus'
Conflicts: drivers/message/fusion/mptsas.c fixed up conflict between req->data_len accessors and mptsas driver updates. Signed-off-by: James Bottomley <James.Bottomley@HansenPartnership.com>
Diffstat (limited to 'arch/sh/include/asm/unaligned-sh4a.h')
-rw-r--r--arch/sh/include/asm/unaligned-sh4a.h10
1 files changed, 5 insertions, 5 deletions
diff --git a/arch/sh/include/asm/unaligned-sh4a.h b/arch/sh/include/asm/unaligned-sh4a.h
index d8f89770275..9f4dd252c98 100644
--- a/arch/sh/include/asm/unaligned-sh4a.h
+++ b/arch/sh/include/asm/unaligned-sh4a.h
@@ -3,9 +3,9 @@
/*
* SH-4A has support for unaligned 32-bit loads, and 32-bit loads only.
- * Support for 16 and 64-bit accesses are done through shifting and
- * masking relative to the endianness. Unaligned stores are not supported
- * by the instruction encoding, so these continue to use the packed
+ * Support for 64-bit accesses are done through shifting and masking
+ * relative to the endianness. Unaligned stores are not supported by the
+ * instruction encoding, so these continue to use the packed
* struct.
*
* The same note as with the movli.l/movco.l pair applies here, as long
@@ -41,9 +41,9 @@ struct __una_u64 { u64 x __attribute__((packed)); };
static inline u16 __get_unaligned_cpu16(const u8 *p)
{
#ifdef __LITTLE_ENDIAN
- return __get_unaligned_cpu32(p) & 0xffff;
+ return p[0] | p[1] << 8;
#else
- return __get_unaligned_cpu32(p) >> 16;
+ return p[0] << 8 | p[1];
#endif
}