diff options
author | James Bottomley <James.Bottomley@HansenPartnership.com> | 2009-06-12 10:02:03 -0500 |
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committer | James Bottomley <James.Bottomley@HansenPartnership.com> | 2009-06-12 10:02:03 -0500 |
commit | 82681a318f9f028ea64e61f24bbd9ac535531921 (patch) | |
tree | 529b6a5b4fd040fb54b7672b1a224ebd47445876 /arch/sh/include/cpu-sh4/cpu/timer.h | |
parent | 3860c97bd60a4525bb62eb90e3e7d2f02662ac59 (diff) | |
parent | 8ebf975608aaebd7feb33d77f07ba21a6380e086 (diff) |
[SCSI] Merge branch 'linus'
Conflicts:
drivers/message/fusion/mptsas.c
fixed up conflict between req->data_len accessors and mptsas driver updates.
Signed-off-by: James Bottomley <James.Bottomley@HansenPartnership.com>
Diffstat (limited to 'arch/sh/include/cpu-sh4/cpu/timer.h')
-rw-r--r-- | arch/sh/include/cpu-sh4/cpu/timer.h | 60 |
1 files changed, 0 insertions, 60 deletions
diff --git a/arch/sh/include/cpu-sh4/cpu/timer.h b/arch/sh/include/cpu-sh4/cpu/timer.h deleted file mode 100644 index d1e796b9688..00000000000 --- a/arch/sh/include/cpu-sh4/cpu/timer.h +++ /dev/null @@ -1,60 +0,0 @@ -/* - * include/asm-sh/cpu-sh4/timer.h - * - * Copyright (C) 2004 Lineo Solutions, Inc. - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - */ -#ifndef __ASM_CPU_SH4_TIMER_H -#define __ASM_CPU_SH4_TIMER_H - -/* - * --------------------------------------------------------------------------- - * TMU Common definitions for SH4 processors - * SH7750S/SH7750R - * SH7751/SH7751R - * SH7760 - * SH-X3 - * --------------------------------------------------------------------------- - */ -#ifdef CONFIG_CPU_SUBTYPE_SHX3 -#define TMU_012_BASE 0xffc10000 -#define TMU_345_BASE 0xffc20000 -#else -#define TMU_012_BASE 0xffd80000 -#define TMU_345_BASE 0xfe100000 -#endif - -#define TMU_TOCR TMU_012_BASE /* Not supported on all CPUs */ - -#define TMU_012_TSTR (TMU_012_BASE + 0x04) -#define TMU_345_TSTR (TMU_345_BASE + 0x04) - -#define TMU0_TCOR (TMU_012_BASE + 0x08) -#define TMU0_TCNT (TMU_012_BASE + 0x0c) -#define TMU0_TCR (TMU_012_BASE + 0x10) - -#define TMU1_TCOR (TMU_012_BASE + 0x14) -#define TMU1_TCNT (TMU_012_BASE + 0x18) -#define TMU1_TCR (TMU_012_BASE + 0x1c) - -#define TMU2_TCOR (TMU_012_BASE + 0x20) -#define TMU2_TCNT (TMU_012_BASE + 0x24) -#define TMU2_TCR (TMU_012_BASE + 0x28) -#define TMU2_TCPR (TMU_012_BASE + 0x2c) - -#define TMU3_TCOR (TMU_345_BASE + 0x08) -#define TMU3_TCNT (TMU_345_BASE + 0x0c) -#define TMU3_TCR (TMU_345_BASE + 0x10) - -#define TMU4_TCOR (TMU_345_BASE + 0x14) -#define TMU4_TCNT (TMU_345_BASE + 0x18) -#define TMU4_TCR (TMU_345_BASE + 0x1c) - -#define TMU5_TCOR (TMU_345_BASE + 0x20) -#define TMU5_TCNT (TMU_345_BASE + 0x24) -#define TMU5_TCR (TMU_345_BASE + 0x28) - -#endif /* __ASM_CPU_SH4_TIMER_H */ |