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authorMagnus Damm <damm@igel.co.jp>2009-06-02 09:45:16 +0000
committerPaul Mundt <lethal@linux-sh.org>2009-06-11 09:09:01 +0300
commite4218ef506a2f8b0b5bf1a4b6effcc2f8983f86b (patch)
tree26145b01af90b23a5f7bf7dc5919b6759be82657 /arch/sh/include
parent0d4fdbb64f472ef31195714993f1263f77cf85ca (diff)
sh: sh7723 mode pin V2
This patch is sh7723 mode pin V2. Mode pins and pin function controller comments are added. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/include')
-rw-r--r--arch/sh/include/cpu-sh4/cpu/sh7723.h14
1 files changed, 14 insertions, 0 deletions
diff --git a/arch/sh/include/cpu-sh4/cpu/sh7723.h b/arch/sh/include/cpu-sh4/cpu/sh7723.h
index 9d2f6d7aa93..14c8ca93678 100644
--- a/arch/sh/include/cpu-sh4/cpu/sh7723.h
+++ b/arch/sh/include/cpu-sh4/cpu/sh7723.h
@@ -1,6 +1,20 @@
#ifndef __ASM_SH7723_H__
#define __ASM_SH7723_H__
+/* Boot Mode Pins:
+ *
+ * MD0: CPG - Clock Mode 0->3
+ * MD1: CPG - Clock Mode 0->3
+ * MD2: CPG - Reserved (L: Normal operation)
+ * MD3: BSC - Area0 Bus Width (16/32-bit) [CS0BCR.9,10]
+ * MD5: BSC - Endian Mode (L: Big, H: Little) [CMNCR.3]
+ * MD8: Test Mode
+ */
+
+/* Pin Function Controller:
+ * GPIO_FN_xx - GPIO used to select pin function
+ * GPIO_Pxx - GPIO mapped to real I/O pin on CPU
+ */
enum {
/* PTA */
GPIO_PTA7, GPIO_PTA6, GPIO_PTA5, GPIO_PTA4,