diff options
author | Kieran Bingham <kieranbingham@gmail.com> | 2009-05-08 15:49:50 +0100 |
---|---|---|
committer | Paul Mundt <lethal@linux-sh.org> | 2009-05-09 00:09:21 +0900 |
commit | e73173dbe55e5b4c2306728aad50c8e42194f6d5 (patch) | |
tree | 3c9eb779f1d376b2bff8d5482717260d26f9981d /arch/sh/include | |
parent | be6514c6295cc79498eeb9a8f933451082ca9e69 (diff) |
sh: Fix UBC setup and registers for SH2A
Signed-off-by: Kieran Bingham <kieranbingham@gmail.com>
Signed-off-by: Peter Griffin <pgriffin@mpc-data.co.uk>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/include')
-rw-r--r-- | arch/sh/include/asm/ubc.h | 11 | ||||
-rw-r--r-- | arch/sh/include/cpu-sh2a/cpu/ubc.h | 29 |
2 files changed, 39 insertions, 1 deletions
diff --git a/arch/sh/include/asm/ubc.h b/arch/sh/include/asm/ubc.h index a7b9028bbfb..4ca4b771737 100644 --- a/arch/sh/include/asm/ubc.h +++ b/arch/sh/include/asm/ubc.h @@ -42,12 +42,23 @@ #define BRCR_CMFA (1 << 15) #define BRCR_CMFB (1 << 14) + +#if defined CONFIG_CPU_SH2A +#define BRCR_CMFCA (1 << 15) +#define BRCR_CMFCB (1 << 14) +#define BRCR_CMFDA (1 << 13) +#define BRCR_CMFDB (1 << 12) +#define BRCR_PCBB (1 << 6) /* 1: after execution */ +#define BRCR_PCBA (1 << 5) /* 1: after execution */ +#define BRCR_PCTE 0 +#else #define BRCR_PCTE (1 << 11) #define BRCR_PCBA (1 << 10) /* 1: after execution */ #define BRCR_DBEB (1 << 7) #define BRCR_PCBB (1 << 6) #define BRCR_SEQ (1 << 3) #define BRCR_UBDE (1 << 0) +#endif #ifndef __ASSEMBLY__ /* arch/sh/kernel/cpu/ubc.S */ diff --git a/arch/sh/include/cpu-sh2a/cpu/ubc.h b/arch/sh/include/cpu-sh2a/cpu/ubc.h index 8ce2fc1cf62..1192e1c761a 100644 --- a/arch/sh/include/cpu-sh2a/cpu/ubc.h +++ b/arch/sh/include/cpu-sh2a/cpu/ubc.h @@ -1 +1,28 @@ -#include <cpu-sh2/cpu/ubc.h> +/* + * SH-2A UBC definitions + * + * Copyright (C) 2008 Kieran Bingham + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ + +#ifndef __ASM_CPU_SH2A_UBC_H +#define __ASM_CPU_SH2A_UBC_H + +#define UBC_BARA 0xfffc0400 +#define UBC_BAMRA 0xfffc0404 +#define UBC_BBRA 0xfffc04a0 /* 16 bit access */ +#define UBC_BDRA 0xfffc0408 +#define UBC_BDMRA 0xfffc040c + +#define UBC_BARB 0xfffc0410 +#define UBC_BAMRB 0xfffc0414 +#define UBC_BBRB 0xfffc04b0 /* 16 bit access */ +#define UBC_BDRB 0xfffc0418 +#define UBC_BDMRB 0xfffc041c + +#define UBC_BRCR 0xfffc04c0 + +#endif /* __ASM_CPU_SH2A_UBC_H */ |