diff options
author | David S. Miller <davem@davemloft.net> | 2009-03-26 15:23:24 -0700 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2009-03-26 15:23:24 -0700 |
commit | 08abe18af1f78ee80c3c3a5ac47c3e0ae0beadf6 (patch) | |
tree | 2be39bf8942edca1bcec735145e144a682ca9cd3 /arch/sh/kernel/cpu/sh2a | |
parent | f0de70f8bb56952f6e016a65a8a8d006918f5bf6 (diff) | |
parent | 0384e2959127a56d0640505d004d8dd92f9c29f5 (diff) |
Merge branch 'master' of /home/davem/src/GIT/linux-2.6/
Conflicts:
drivers/net/wimax/i2400m/usb-notif.c
Diffstat (limited to 'arch/sh/kernel/cpu/sh2a')
-rw-r--r-- | arch/sh/kernel/cpu/sh2a/setup-mxg.c | 65 | ||||
-rw-r--r-- | arch/sh/kernel/cpu/sh2a/setup-sh7201.c | 224 | ||||
-rw-r--r-- | arch/sh/kernel/cpu/sh2a/setup-sh7203.c | 236 | ||||
-rw-r--r-- | arch/sh/kernel/cpu/sh2a/setup-sh7206.c | 154 |
4 files changed, 241 insertions, 438 deletions
diff --git a/arch/sh/kernel/cpu/sh2a/setup-mxg.c b/arch/sh/kernel/cpu/sh2a/setup-mxg.c index e611d79fac4..844293723cf 100644 --- a/arch/sh/kernel/cpu/sh2a/setup-mxg.c +++ b/arch/sh/kernel/cpu/sh2a/setup-mxg.c @@ -1,7 +1,7 @@ /* * Renesas MX-G (R8A03022BG) Setup * - * Copyright (C) 2008 Paul Mundt + * Copyright (C) 2008, 2009 Paul Mundt * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive @@ -20,23 +20,15 @@ enum { IRQ8, IRQ9, IRQ10, IRQ11, IRQ12, IRQ13, IRQ14, IRQ15, PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7, - SINT8, SINT7, SINT6, SINT5, SINT4, SINT3, SINT2, SINT1, - SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI, - SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI, + SCIF0, SCIF1, - MTU2_TGI0A, MTU2_TGI0B, MTU2_TGI0C, MTU2_TGI0D, - MTU2_TCI0V, MTU2_TGI0E, MTU2_TGI0F, - MTU2_TGI1A, MTU2_TGI1B, MTU2_TCI1V, MTU2_TCI1U, - MTU2_TGI2A, MTU2_TGI2B, MTU2_TCI2V, MTU2_TCI2U, - MTU2_TGI3A, MTU2_TGI3B, MTU2_TGI3C, MTU2_TGI3D, MTU2_TCI3V, - MTU2_TGI4A, MTU2_TGI4B, MTU2_TGI4C, MTU2_TGI4D, MTU2_TCI4V, - MTU2_TGI5U, MTU2_TGI5V, MTU2_TGI5W, + MTU2_GROUP1, MTU2_GROUP2, MTU2_GROUP3, MTU2_GROUP4, MTU2_GROUP5 + MTU2_TGI3B, MTU2_TGI3C, /* interrupt groups */ - PINT, SCIF0, SCIF1, - MTU2_GROUP1, MTU2_GROUP2, MTU2_GROUP3, MTU2_GROUP4, MTU2_GROUP5 + PINT, }; static struct intc_vect vectors[] __initdata = { @@ -59,47 +51,36 @@ static struct intc_vect vectors[] __initdata = { INTC_IRQ(SINT4, 98), INTC_IRQ(SINT3, 99), INTC_IRQ(SINT2, 100), INTC_IRQ(SINT1, 101), - INTC_IRQ(SCIF0_RXI, 220), INTC_IRQ(SCIF0_TXI, 221), - INTC_IRQ(SCIF0_BRI, 222), INTC_IRQ(SCIF0_ERI, 223), - INTC_IRQ(SCIF1_RXI, 224), INTC_IRQ(SCIF1_TXI, 225), - INTC_IRQ(SCIF1_BRI, 226), INTC_IRQ(SCIF1_ERI, 227), + INTC_IRQ(SCIF0, 220), INTC_IRQ(SCIF0, 221), + INTC_IRQ(SCIF0, 222), INTC_IRQ(SCIF0, 223), + INTC_IRQ(SCIF1, 224), INTC_IRQ(SCIF1, 225), + INTC_IRQ(SCIF1, 226), INTC_IRQ(SCIF1, 227), - INTC_IRQ(MTU2_TGI0A, 228), INTC_IRQ(MTU2_TGI0B, 229), - INTC_IRQ(MTU2_TGI0C, 230), INTC_IRQ(MTU2_TGI0D, 231), - INTC_IRQ(MTU2_TCI0V, 232), INTC_IRQ(MTU2_TGI0E, 233), + INTC_IRQ(MTU2_GROUP1, 228), INTC_IRQ(MTU2_GROUP1, 229), + INTC_IRQ(MTU2_GROUP1, 230), INTC_IRQ(MTU2_GROUP1, 231), + INTC_IRQ(MTU2_GROUP1, 232), INTC_IRQ(MTU2_GROUP1, 233), - INTC_IRQ(MTU2_TGI0F, 234), INTC_IRQ(MTU2_TGI1A, 235), - INTC_IRQ(MTU2_TGI1B, 236), INTC_IRQ(MTU2_TCI1V, 237), - INTC_IRQ(MTU2_TCI1U, 238), INTC_IRQ(MTU2_TGI2A, 239), + INTC_IRQ(MTU2_GROUP2, 234), INTC_IRQ(MTU2_GROUP2, 235), + INTC_IRQ(MTU2_GROUP2, 236), INTC_IRQ(MTU2_GROUP2, 237), + INTC_IRQ(MTU2_GROUP2, 238), INTC_IRQ(MTU2_GROUP2, 239), - INTC_IRQ(MTU2_TGI2B, 240), INTC_IRQ(MTU2_TCI2V, 241), - INTC_IRQ(MTU2_TCI2U, 242), INTC_IRQ(MTU2_TGI3A, 243), + INTC_IRQ(MTU2_GROUP3, 240), INTC_IRQ(MTU2_GROUP3, 241), + INTC_IRQ(MTU2_GROUP3, 242), INTC_IRQ(MTU2_GROUP3, 243), INTC_IRQ(MTU2_TGI3B, 244), INTC_IRQ(MTU2_TGI3C, 245), - INTC_IRQ(MTU2_TGI3D, 246), INTC_IRQ(MTU2_TCI3V, 247), - INTC_IRQ(MTU2_TGI4A, 248), INTC_IRQ(MTU2_TGI4B, 249), - INTC_IRQ(MTU2_TGI4C, 250), INTC_IRQ(MTU2_TGI4D, 251), + INTC_IRQ(MTU2_GROUP4, 246), INTC_IRQ(MTU2_GROUP4, 247), + INTC_IRQ(MTU2_GROUP4, 248), INTC_IRQ(MTU2_GROUP4, 249), + INTC_IRQ(MTU2_GROUP4, 250), INTC_IRQ(MTU2_GROUP4, 251), - INTC_IRQ(MTU2_TCI4V, 252), INTC_IRQ(MTU2_TGI5U, 253), - INTC_IRQ(MTU2_TGI5V, 254), INTC_IRQ(MTU2_TGI5W, 255), + INTC_IRQ(MTU2_GROUP5, 252), INTC_IRQ(MTU2_GROUP5, 253), + INTC_IRQ(MTU2_GROUP5, 254), INTC_IRQ(MTU2_GROUP5, 255), }; static struct intc_group groups[] __initdata = { INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7), - INTC_GROUP(MTU2_GROUP1, MTU2_TGI0A, MTU2_TGI0B, MTU2_TGI0C, MTU2_TGI0D, - MTU2_TCI0V, MTU2_TGI0E), - INTC_GROUP(MTU2_GROUP2, MTU2_TGI0F, MTU2_TGI1A, MTU2_TGI1B, - MTU2_TCI1V, MTU2_TCI1U, MTU2_TGI2A), - INTC_GROUP(MTU2_GROUP3, MTU2_TGI2B, MTU2_TCI2V, MTU2_TCI2U, - MTU2_TGI3A), - INTC_GROUP(MTU2_GROUP4, MTU2_TGI3D, MTU2_TCI3V, MTU2_TGI4A, - MTU2_TGI4B, MTU2_TGI4C, MTU2_TGI4D), - INTC_GROUP(MTU2_GROUP5, MTU2_TCI4V, MTU2_TGI5U, MTU2_TGI5V, MTU2_TGI5W), - INTC_GROUP(SCIF0, SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI), - INTC_GROUP(SCIF1, SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI), }; static struct intc_prio_reg prio_registers[] __initdata = { @@ -137,7 +118,7 @@ static struct plat_sci_port sci_platform_data[] = { .mapbase = 0xff804000, .flags = UPF_BOOT_AUTOCONF, .type = PORT_SCIF, - .irqs = { 223, 220, 221, 222 }, + .irqs = { 220, 220, 220, 220 }, }, { .flags = 0, } diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7201.c b/arch/sh/kernel/cpu/sh2a/setup-sh7201.c index 0631e421c02..00f42f9e3f5 100644 --- a/arch/sh/kernel/cpu/sh2a/setup-sh7201.c +++ b/arch/sh/kernel/cpu/sh2a/setup-sh7201.c @@ -2,6 +2,7 @@ * SH7201 setup * * Copyright (C) 2008 Peter Griffin pgriffin@mpc-data.co.uk + * Copyright (C) 2009 Paul Mundt * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive @@ -18,57 +19,32 @@ enum { /* interrupt sources */ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7, + ADC_ADI, - MTU2_TGI0A, MTU2_TGI0B, MTU2_TGI0C, MTU2_TGI0D, - MTU2_TCI0V, MTU2_TGI0E, MTU2_TGI0F, - MTU2_TGI1A, MTU2_TGI1B, MTU2_TCI1V, MTU2_TCI1U, - MTU2_TGI2A, MTU2_TGI2B, MTU2_TCI2V, MTU2_TCI2U, - MTU2_TGI3A, MTU2_TGI3B, MTU2_TGI3C, MTU2_TGI3D, MTU2_TCI3V, - MTU2_TGI4A, MTU2_TGI4B, MTU2_TGI4C, MTU2_TGI4D, MTU2_TCI4V, - MTU2_TGI5U, MTU2_TGI5V, MTU2_TGI5W, - RTC_ARM, RTC_PRD, RTC_CUP, - WDT, - IIC30_STPI, IIC30_NAKI, IIC30_RXI, IIC30_TXI, IIC30_TEI, - IIC31_STPI, IIC31_NAKI, IIC31_RXI, IIC31_TXI, IIC31_TEI, - IIC32_STPI, IIC32_NAKI, IIC32_RXI, IIC32_TXI, IIC32_TEI, + + MTU20_ABCD, MTU20_VEF, MTU21_AB, MTU21_VU, MTU22_AB, MTU22_VU, + MTU23_ABCD, MTU24_ABCD, MTU25_UVW, MTU2_TCI3V, MTU2_TCI4V, + + RTC, WDT, + + IIC30, IIC31, IIC32, DMAC0_DMINT0, DMAC1_DMINT1, DMAC2_DMINT2, DMAC3_DMINT3, - SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI, - SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI, - SCIF2_BRI, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI, - SCIF3_BRI, SCIF3_ERI, SCIF3_RXI, SCIF3_TXI, - SCIF4_BRI, SCIF4_ERI, SCIF4_RXI, SCIF4_TXI, - SCIF5_BRI, SCIF5_ERI, SCIF5_RXI, SCIF5_TXI, - SCIF6_BRI, SCIF6_ERI, SCIF6_RXI, SCIF6_TXI, - SCIF7_BRI, SCIF7_ERI, SCIF7_RXI, SCIF7_TXI, + SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, SCIF5, SCIF6, SCIF7, DMAC0_DMINTA, DMAC4_DMINT4, DMAC5_DMINT5, DMAC6_DMINT6, DMAC7_DMINT7, - RCAN0_ERS, RCAN0_OVR, - RCAN0_SLE, - RCAN0_RM0, RCAN0_RM1, - - RCAN1_ERS, RCAN1_OVR, - RCAN1_SLE, - RCAN1_RM0, RCAN1_RM1, + RCAN0, RCAN1, SSI0_SSII, SSI1_SSII, - TMR0_CMIA0, TMR0_CMIB0, TMR0_OVI0, - TMR1_CMIA1, TMR1_CMIB1, TMR1_OVI1, + TMR0, TMR1, /* interrupt groups */ - - IRQ, PINT, ADC, - MTU20_ABCD, MTU20_VEF, MTU21_AB, MTU21_VU, MTU22_AB, MTU22_VU, - MTU23_ABCD, MTU24_ABCD, MTU25_UVW, - RTC, IIC30, IIC31, IIC32, - SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, SCIF5, SCIF6, SCIF7, - RCAN0, RCAN1, TMR0, TMR1 - + PINT, }; static struct intc_vect vectors[] __initdata = { @@ -76,6 +52,7 @@ static struct intc_vect vectors[] __initdata = { INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67), INTC_IRQ(IRQ4, 68), INTC_IRQ(IRQ5, 69), INTC_IRQ(IRQ6, 70), INTC_IRQ(IRQ7, 71), + INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81), INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83), INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85), @@ -83,123 +60,92 @@ static struct intc_vect vectors[] __initdata = { INTC_IRQ(ADC_ADI, 92), - INTC_IRQ(MTU2_TGI0A, 108), INTC_IRQ(MTU2_TGI0B, 109), - INTC_IRQ(MTU2_TGI0C, 110), INTC_IRQ(MTU2_TGI0D, 111), - INTC_IRQ(MTU2_TCI0V, 112), - INTC_IRQ(MTU2_TGI0E, 113), INTC_IRQ(MTU2_TGI0F, 114), + INTC_IRQ(MTU20_ABCD, 108), INTC_IRQ(MTU20_ABCD, 109), + INTC_IRQ(MTU20_ABCD, 110), INTC_IRQ(MTU20_ABCD, 111), + + INTC_IRQ(MTU20_VEF, 112), INTC_IRQ(MTU20_VEF, 113), + INTC_IRQ(MTU20_VEF, 114), + + INTC_IRQ(MTU21_AB, 116), INTC_IRQ(MTU21_AB, 117), + INTC_IRQ(MTU21_VU, 120), INTC_IRQ(MTU21_VU, 121), - INTC_IRQ(MTU2_TGI1A, 116), INTC_IRQ(MTU2_TGI1B, 117), - INTC_IRQ(MTU2_TCI1V, 120), INTC_IRQ(MTU2_TCI1U, 121), + INTC_IRQ(MTU22_AB, 124), INTC_IRQ(MTU22_AB, 125), + INTC_IRQ(MTU22_VU, 128), INTC_IRQ(MTU22_VU, 129), - INTC_IRQ(MTU2_TGI2A, 124), INTC_IRQ(MTU2_TGI2B, 125), - INTC_IRQ(MTU2_TCI2V, 128), INTC_IRQ(MTU2_TCI2U, 129), + INTC_IRQ(MTU23_ABCD, 132), INTC_IRQ(MTU23_ABCD, 133), + INTC_IRQ(MTU23_ABCD, 134), INTC_IRQ(MTU23_ABCD, 135), - INTC_IRQ(MTU2_TGI3A, 132), INTC_IRQ(MTU2_TGI3B, 133), - INTC_IRQ(MTU2_TGI3C, 134), INTC_IRQ(MTU2_TGI3D, 135), INTC_IRQ(MTU2_TCI3V, 136), - INTC_IRQ(MTU2_TGI4A, 140), INTC_IRQ(MTU2_TGI4B, 141), - INTC_IRQ(MTU2_TGI4C, 142), INTC_IRQ(MTU2_TGI4D, 143), + INTC_IRQ(MTU24_ABCD, 140), INTC_IRQ(MTU24_ABCD, 141), + INTC_IRQ(MTU24_ABCD, 142), INTC_IRQ(MTU24_ABCD, 143), + INTC_IRQ(MTU2_TCI4V, 144), - INTC_IRQ(MTU2_TGI5U, 148), INTC_IRQ(MTU2_TGI5V, 149), - INTC_IRQ(MTU2_TGI5W, 150), + INTC_IRQ(MTU25_UVW, 148), INTC_IRQ(MTU25_UVW, 149), + INTC_IRQ(MTU25_UVW, 150), + + INTC_IRQ(RTC, 152), INTC_IRQ(RTC, 153), + INTC_IRQ(RTC, 154), - INTC_IRQ(RTC_ARM, 152), INTC_IRQ(RTC_PRD, 153), - INTC_IRQ(RTC_CUP, 154), INTC_IRQ(WDT, 156), + INTC_IRQ(WDT, 156), - INTC_IRQ(IIC30_STPI, 157), INTC_IRQ(IIC30_NAKI, 158), - INTC_IRQ(IIC30_RXI, 159), INTC_IRQ(IIC30_TXI, 160), - INTC_IRQ(IIC30_TEI, 161), + INTC_IRQ(IIC30, 157), INTC_IRQ(IIC30, 158), + INTC_IRQ(IIC30, 159), INTC_IRQ(IIC30, 160), + INTC_IRQ(IIC30, 161), - INTC_IRQ(IIC31_STPI, 164), INTC_IRQ(IIC31_NAKI, 165), - INTC_IRQ(IIC31_RXI, 166), INTC_IRQ(IIC31_TXI, 167), - INTC_IRQ(IIC31_TEI, 168), + INTC_IRQ(IIC31, 164), INTC_IRQ(IIC31, 165), + INTC_IRQ(IIC31, 166), INTC_IRQ(IIC31, 167), + INTC_IRQ(IIC31, 168), - INTC_IRQ(IIC32_STPI, 170), INTC_IRQ(IIC32_NAKI, 171), - INTC_IRQ(IIC32_RXI, 172), INTC_IRQ(IIC32_TXI, 173), - INTC_IRQ(IIC32_TEI, 174), + INTC_IRQ(IIC32, 170), INTC_IRQ(IIC32, 171), + INTC_IRQ(IIC32, 172), INTC_IRQ(IIC32, 173), + INTC_IRQ(IIC32, 174), INTC_IRQ(DMAC0_DMINT0, 176), INTC_IRQ(DMAC1_DMINT1, 177), INTC_IRQ(DMAC2_DMINT2, 178), INTC_IRQ(DMAC3_DMINT3, 179), - INTC_IRQ(SCIF0_BRI, 180), INTC_IRQ(SCIF0_ERI, 181), - INTC_IRQ(SCIF0_RXI, 182), INTC_IRQ(SCIF0_TXI, 183), - INTC_IRQ(SCIF1_BRI, 184), INTC_IRQ(SCIF1_ERI, 185), - INTC_IRQ(SCIF1_RXI, 186), INTC_IRQ(SCIF1_TXI, 187), - INTC_IRQ(SCIF2_BRI, 188), INTC_IRQ(SCIF2_ERI, 189), - INTC_IRQ(SCIF2_RXI, 190), INTC_IRQ(SCIF2_TXI, 191), - INTC_IRQ(SCIF3_BRI, 192), INTC_IRQ(SCIF3_ERI, 193), - INTC_IRQ(SCIF3_RXI, 194), INTC_IRQ(SCIF3_TXI, 195), - INTC_IRQ(SCIF4_BRI, 196), INTC_IRQ(SCIF4_ERI, 197), - INTC_IRQ(SCIF4_RXI, 198), INTC_IRQ(SCIF4_TXI, 199), - INTC_IRQ(SCIF5_BRI, 200), INTC_IRQ(SCIF5_ERI, 201), - INTC_IRQ(SCIF5_RXI, 202), INTC_IRQ(SCIF5_TXI, 203), - INTC_IRQ(SCIF6_BRI, 204), INTC_IRQ(SCIF6_ERI, 205), - INTC_IRQ(SCIF6_RXI, 206), INTC_IRQ(SCIF6_TXI, 207), - INTC_IRQ(SCIF7_BRI, 208), INTC_IRQ(SCIF7_ERI, 209), - INTC_IRQ(SCIF7_RXI, 210), INTC_IRQ(SCIF7_TXI, 211), + INTC_IRQ(SCIF0, 180), INTC_IRQ(SCIF0, 181), + INTC_IRQ(SCIF0, 182), INTC_IRQ(SCIF0, 183), + INTC_IRQ(SCIF1, 184), INTC_IRQ(SCIF1, 185), + INTC_IRQ(SCIF1, 186), INTC_IRQ(SCIF1, 187), + INTC_IRQ(SCIF2, 188), INTC_IRQ(SCIF2, 189), + INTC_IRQ(SCIF2, 190), INTC_IRQ(SCIF2, 191), + INTC_IRQ(SCIF3, 192), INTC_IRQ(SCIF3, 193), + INTC_IRQ(SCIF3, 194), INTC_IRQ(SCIF3, 195), + INTC_IRQ(SCIF4, 196), INTC_IRQ(SCIF4, 197), + INTC_IRQ(SCIF4, 198), INTC_IRQ(SCIF4, 199), + INTC_IRQ(SCIF5, 200), INTC_IRQ(SCIF5, 201), + INTC_IRQ(SCIF5, 202), INTC_IRQ(SCIF5, 203), + INTC_IRQ(SCIF6, 204), INTC_IRQ(SCIF6, 205), + INTC_IRQ(SCIF6, 206), INTC_IRQ(SCIF6, 207), + INTC_IRQ(SCIF7, 208), INTC_IRQ(SCIF7, 209), + INTC_IRQ(SCIF7, 210), INTC_IRQ(SCIF7, 211), INTC_IRQ(DMAC0_DMINTA, 212), INTC_IRQ(DMAC4_DMINT4, 216), INTC_IRQ(DMAC5_DMINT5, 217), INTC_IRQ(DMAC6_DMINT6, 218), INTC_IRQ(DMAC7_DMINT7, 219), - INTC_IRQ(RCAN0_ERS, 228), INTC_IRQ(RCAN0_OVR, 229), - INTC_IRQ(RCAN0_SLE, 230), - INTC_IRQ(RCAN0_RM0, 231), INTC_IRQ(RCAN0_RM1, 232), + INTC_IRQ(RCAN0, 228), INTC_IRQ(RCAN0, 229), + INTC_IRQ(RCAN0, 230), + INTC_IRQ(RCAN0, 231), INTC_IRQ(RCAN0, 232), - INTC_IRQ(RCAN1_ERS, 234), INTC_IRQ(RCAN1_OVR, 235), - INTC_IRQ(RCAN1_SLE, 236), - INTC_IRQ(RCAN1_RM0, 237), INTC_IRQ(RCAN1_RM1, 238), + INTC_IRQ(RCAN1, 234), INTC_IRQ(RCAN1, 235), + INTC_IRQ(RCAN1, 236), + INTC_IRQ(RCAN1, 237), INTC_IRQ(RCAN1, 238), INTC_IRQ(SSI0_SSII, 244), INTC_IRQ(SSI1_SSII, 245), - INTC_IRQ(TMR0_CMIA0, 246), INTC_IRQ(TMR0_CMIB0, 247), - INTC_IRQ(TMR0_OVI0, 248), - - INTC_IRQ(TMR1_CMIA1, 252), INTC_IRQ(TMR1_CMIB1, 253), - INTC_IRQ(TMR1_OVI1, 254), + INTC_IRQ(TMR0, 246), INTC_IRQ(TMR0, 247), + INTC_IRQ(TMR0, 248), + INTC_IRQ(TMR1, 252), INTC_IRQ(TMR1, 253), + INTC_IRQ(TMR1, 254), }; static struct intc_group groups[] __initdata = { INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7), - INTC_GROUP(MTU20_ABCD, MTU2_TGI0A, MTU2_TGI0B, MTU2_TGI0C, MTU2_TGI0D), - INTC_GROUP(MTU20_VEF, MTU2_TCI0V, MTU2_TGI0E, MTU2_TGI0F), - - INTC_GROUP(MTU21_AB, MTU2_TGI1A, MTU2_TGI1B), - INTC_GROUP(MTU21_VU, MTU2_TCI1V, MTU2_TCI1U), - INTC_GROUP(MTU22_AB, MTU2_TGI2A, MTU2_TGI2B), - INTC_GROUP(MTU22_VU, MTU2_TCI2V, MTU2_TCI2U), - INTC_GROUP(MTU23_ABCD, MTU2_TGI3A, MTU2_TGI3B, MTU2_TGI3C, MTU2_TGI3D), - INTC_GROUP(MTU24_ABCD, MTU2_TGI4A, MTU2_TGI4B, MTU2_TGI4C, MTU2_TGI4D), - INTC_GROUP(MTU25_UVW, MTU2_TGI5U, MTU2_TGI5V, MTU2_TGI5W), - INTC_GROUP(RTC, RTC_ARM, RTC_PRD, RTC_CUP ), - - INTC_GROUP(IIC30, IIC30_STPI, IIC30_NAKI, IIC30_RXI, IIC30_TXI, - IIC30_TEI), - INTC_GROUP(IIC31, IIC31_STPI, IIC31_NAKI, IIC31_RXI, IIC31_TXI, - IIC31_TEI), - INTC_GROUP(IIC32, IIC32_STPI, IIC32_NAKI, IIC32_RXI, IIC32_TXI, - IIC32_TEI), - - INTC_GROUP(SCIF0, SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI), - INTC_GROUP(SCIF1, SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI), - INTC_GROUP(SCIF2, SCIF2_BRI, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI), - INTC_GROUP(SCIF3, SCIF3_BRI, SCIF3_ERI, SCIF3_RXI, SCIF3_TXI), - INTC_GROUP(SCIF4, SCIF4_BRI, SCIF4_ERI, SCIF4_RXI, SCIF4_TXI), - INTC_GROUP(SCIF5, SCIF5_BRI, SCIF5_ERI, SCIF5_RXI, SCIF5_TXI), - INTC_GROUP(SCIF6, SCIF6_BRI, SCIF6_ERI, SCIF6_RXI, SCIF6_TXI), - INTC_GROUP(SCIF7, SCIF7_BRI, SCIF7_ERI, SCIF7_RXI, SCIF7_TXI), - - INTC_GROUP(RCAN0, RCAN0_ERS, RCAN0_OVR, RCAN0_RM0, RCAN0_RM1, - RCAN0_SLE), - INTC_GROUP(RCAN1, RCAN1_ERS, RCAN1_OVR, RCAN1_RM0, RCAN1_RM1, - RCAN1_SLE), - - INTC_GROUP(TMR0, TMR0_CMIA0, TMR0_CMIB0, TMR0_OVI0), - INTC_GROUP(TMR1, TMR1_CMIA1, TMR1_CMIB1, TMR1_OVI1), }; static struct intc_prio_reg prio_registers[] __initdata = { @@ -212,7 +158,7 @@ static struct intc_prio_reg prio_registers[] __initdata = { { 0xfffe9806, 0, 16, 4, /* IPR09 */ { RTC, WDT, IIC30, 0 } }, { 0xfffe9808, 0, 16, 4, /* IPR10 */ { IIC31, IIC32, DMAC0_DMINT0, DMAC1_DMINT1 } }, - { 0xfffe980a, 0, 16, 4, /* IPR11 */ { DMAC2_DMINT2, DMAC3_DMINT3, SCIF0 , SCIF1 } }, + { 0xfffe980a, 0, 16, 4, /* IPR11 */ { DMAC2_DMINT2, DMAC3_DMINT3, SCIF0, SCIF1 } }, { 0xfffe980c, 0, 16, 4, /* IPR12 */ { SCIF2, SCIF3, SCIF4, SCIF5 } }, { 0xfffe980e, 0, 16, 4, /* IPR13 */ { SCIF6, SCIF7, DMAC0_DMINTA, DMAC4_DMINT4 } }, { 0xfffe9810, 0, 16, 4, /* IPR14 */ { DMAC5_DMINT5, DMAC6_DMINT6, DMAC7_DMINT7, 0 } }, @@ -234,42 +180,42 @@ static struct plat_sci_port sci_platform_data[] = { .mapbase = 0xfffe8000, .flags = UPF_BOOT_AUTOCONF, .type = PORT_SCIF, - .irqs = { 181, 182, 183, 180} + .irqs = { 180, 180, 180, 180 } }, { .mapbase = 0xfffe8800, .flags = UPF_BOOT_AUTOCONF, .type = PORT_SCIF, - .irqs = { 185, 186, 187, 184} + .irqs = { 184, 184, 184, 184 } }, { .mapbase = 0xfffe9000, .flags = UPF_BOOT_AUTOCONF, .type = PORT_SCIF, - .irqs = { 189, 186, 187, 188} + .irqs = { 188, 188, 188, 188 } }, { .mapbase = 0xfffe9800, .flags = UPF_BOOT_AUTOCONF, .type = PORT_SCIF, - .irqs = { 193, 194, 195, 192} + .irqs = { 192, 192, 192, 192 } }, { .mapbase = 0xfffea000, .flags = UPF_BOOT_AUTOCONF, .type = PORT_SCIF, - .irqs = { 196, 198, 199, 196} + .irqs = { 196, 196, 196, 196 } }, { .mapbase = 0xfffea800, .flags = UPF_BOOT_AUTOCONF, .type = PORT_SCIF, - .irqs = { 201, 202, 203, 200} + .irqs = { 200, 200, 200, 200 } }, { .mapbase = 0xfffeb000, .flags = UPF_BOOT_AUTOCONF, .type = PORT_SCIF, - .irqs = { 205, 206, 207, 204} + .irqs = { 204, 204, 204, 204 } }, { .mapbase = 0xfffeb800, .flags = UPF_BOOT_AUTOCONF, .type = PORT_SCIF, - .irqs = { 209, 210, 211, 208} + .irqs = { 208, 208, 208, 208 } }, { .flags = 0, } @@ -290,17 +236,7 @@ static struct resource rtc_resources[] = { .flags = IORESOURCE_IO, }, [1] = { - /* Period IRQ */ - .start = 153, - .flags = IORESOURCE_IRQ, - }, - [2] = { - /* Carry IRQ */ - .start = 154, - .flags = IORESOURCE_IRQ, - }, - [3] = { - /* Alarm IRQ */ + /* Shared Period/Carry/Alarm IRQ */ .start = 152, .flags = IORESOURCE_IRQ, }, diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7203.c b/arch/sh/kernel/cpu/sh2a/setup-sh7203.c index e98dc445035..820dfb2e865 100644 --- a/arch/sh/kernel/cpu/sh2a/setup-sh7203.c +++ b/arch/sh/kernel/cpu/sh2a/setup-sh7203.c @@ -1,7 +1,7 @@ /* * SH7203 and SH7263 Setup * - * Copyright (C) 2007 Paul Mundt + * Copyright (C) 2007 - 2009 Paul Mundt * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive @@ -18,50 +18,27 @@ enum { /* interrupt sources */ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7, - DMAC0_DEI, DMAC0_HEI, DMAC1_DEI, DMAC1_HEI, - DMAC2_DEI, DMAC2_HEI, DMAC3_DEI, DMAC3_HEI, - DMAC4_DEI, DMAC4_HEI, DMAC5_DEI, DMAC5_HEI, - DMAC6_DEI, DMAC6_HEI, DMAC7_DEI, DMAC7_HEI, + DMAC0, DMAC1, DMAC2, DMAC3, DMAC4, DMAC5, DMAC6, DMAC7, USB, LCDC, CMT0, CMT1, BSC, WDT, - MTU2_TGI0A, MTU2_TGI0B, MTU2_TGI0C, MTU2_TGI0D, - MTU2_TCI0V, MTU2_TGI0E, MTU2_TGI0F, - MTU2_TGI1A, MTU2_TGI1B, MTU2_TCI1V, MTU2_TCI1U, - MTU2_TGI2A, MTU2_TGI2B, MTU2_TCI2V, MTU2_TCI2U, - MTU2_TGI3A, MTU2_TGI3B, MTU2_TGI3C, MTU2_TGI3D, MTU2_TCI3V, - MTU2_TGI4A, MTU2_TGI4B, MTU2_TGI4C, MTU2_TGI4D, MTU2_TCI4V, - ADC_ADI, - IIC30_STPI, IIC30_NAKI, IIC30_RXI, IIC30_TXI, IIC30_TEI, - IIC31_STPI, IIC31_NAKI, IIC31_RXI, IIC31_TXI, IIC31_TEI, - IIC32_STPI, IIC32_NAKI, IIC32_RXI, IIC32_TXI, IIC32_TEI, - IIC33_STPI, IIC33_NAKI, IIC33_RXI, IIC33_TXI, IIC33_TEI, - SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI, - SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI, - SCIF2_BRI, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI, - SCIF3_BRI, SCIF3_ERI, SCIF3_RXI, SCIF3_TXI, - SSU0_SSERI, SSU0_SSRXI, SSU0_SSTXI, - SSU1_SSERI, SSU1_SSRXI, SSU1_SSTXI, - SSI0_SSII, SSI1_SSII, SSI2_SSII, SSI3_SSII, - /* ROM-DEC, SDHI, SRC, and IEB are SH7263 specific */ - ROMDEC_ISY, ROMDEC_IERR, ROMDEC_IARG, ROMDEC_ISEC, ROMDEC_IBUF, - ROMDEC_IREADY, + MTU0_ABCD, MTU0_VEF, MTU1_AB, MTU1_VU, MTU2_AB, MTU2_VU, + MTU3_ABCD, MTU4_ABCD, MTU2_TCI3V, MTU2_TCI4V, - FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I, + ADC_ADI, + + IIC30, IIC31, IIC32, IIC33, + SCIF0, SCIF1, SCIF2, SCIF3, - SDHI3, SDHI0, SDHI1, + SSU0, SSU1, - RTC_ARM, RTC_PRD, RTC_CUP, - RCAN0_ERS, RCAN0_OVR, RCAN0_RM0, RCAN0_RM1, RCAN0_SLE, - RCAN1_ERS, RCAN1_OVR, RCAN1_RM0, RCAN1_RM1, RCAN1_SLE, + SSI0_SSII, SSI1_SSII, SSI2_SSII, SSI3_SSII, - SRC_OVF, SRC_ODFI, SRC_IDEI, IEBI, + /* ROM-DEC, SDHI, SRC, and IEB are SH7263 specific */ + ROMDEC, FLCTL, SDHI, RTC, RCAN0, RCAN1, + SRC, IEBI, /* interrupt groups */ - PINT, DMAC0, DMAC1, DMAC2, DMAC3, DMAC4, DMAC5, DMAC6, DMAC7, - MTU0_ABCD, MTU0_VEF, MTU1_AB, MTU1_VU, MTU2_AB, MTU2_VU, - MTU3_ABCD, MTU4_ABCD, - IIC30, IIC31, IIC32, IIC33, SCIF0, SCIF1, SCIF2, SCIF3, - SSU0, SSU1, ROMDEC, SDHI, FLCTL, RTC, RCAN0, RCAN1, SRC + PINT, }; static struct intc_vect vectors[] __initdata = { @@ -73,79 +50,80 @@ static struct intc_vect vectors[] __initdata = { INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83), INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85), INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87), - INTC_IRQ(DMAC0_DEI, 108), INTC_IRQ(DMAC0_HEI, 109), - INTC_IRQ(DMAC1_DEI, 112), INTC_IRQ(DMAC1_HEI, 113), - INTC_IRQ(DMAC2_DEI, 116), INTC_IRQ(DMAC2_HEI, 117), - INTC_IRQ(DMAC3_DEI, 120), INTC_IRQ(DMAC3_HEI, 121), - INTC_IRQ(DMAC4_DEI, 124), INTC_IRQ(DMAC4_HEI, 125), - INTC_IRQ(DMAC5_DEI, 128), INTC_IRQ(DMAC5_HEI, 129), - INTC_IRQ(DMAC6_DEI, 132), INTC_IRQ(DMAC6_HEI, 133), - INTC_IRQ(DMAC7_DEI, 136), INTC_IRQ(DMAC7_HEI, 137), + INTC_IRQ(DMAC0, 108), INTC_IRQ(DMAC0, 109), + INTC_IRQ(DMAC1, 112), INTC_IRQ(DMAC1, 113), + INTC_IRQ(DMAC2, 116), INTC_IRQ(DMAC2, 117), + INTC_IRQ(DMAC3, 120), INTC_IRQ(DMAC3, 121), + INTC_IRQ(DMAC4, 124), INTC_IRQ(DMAC4, 125), + INTC_IRQ(DMAC5, 128), INTC_IRQ(DMAC5, 129), + INTC_IRQ(DMAC6, 132), INTC_IRQ(DMAC6, 133), + INTC_IRQ(DMAC7, 136), INTC_IRQ(DMAC7, 137), INTC_IRQ(USB, 140), INTC_IRQ(LCDC, 141), INTC_IRQ(CMT0, 142), INTC_IRQ(CMT1, 143), INTC_IRQ(BSC, 144), INTC_IRQ(WDT, 145), - INTC_IRQ(MTU2_TGI0A, 146), INTC_IRQ(MTU2_TGI0B, 147), - INTC_IRQ(MTU2_TGI0C, 148), INTC_IRQ(MTU2_TGI0D, 149), - INTC_IRQ(MTU2_TCI0V, 150), - INTC_IRQ(MTU2_TGI0E, 151), INTC_IRQ(MTU2_TGI0F, 152), - INTC_IRQ(MTU2_TGI1A, 153), INTC_IRQ(MTU2_TGI1B, 154), - INTC_IRQ(MTU2_TCI1V, 155), INTC_IRQ(MTU2_TCI1U, 156), - INTC_IRQ(MTU2_TGI2A, 157), INTC_IRQ(MTU2_TGI2B, 158), - INTC_IRQ(MTU2_TCI2V, 159), INTC_IRQ(MTU2_TCI2U, 160), - INTC_IRQ(MTU2_TGI3A, 161), INTC_IRQ(MTU2_TGI3B, 162), - INTC_IRQ(MTU2_TGI3C, 163), INTC_IRQ(MTU2_TGI3D, 164), + INTC_IRQ(MTU0_ABCD, 146), INTC_IRQ(MTU0_ABCD, 147), + INTC_IRQ(MTU0_ABCD, 148), INTC_IRQ(MTU0_ABCD, 149), + INTC_IRQ(MTU0_VEF, 150), + INTC_IRQ(MTU0_VEF, 151), INTC_IRQ(MTU0_VEF, 152), + INTC_IRQ(MTU1_AB, 153), INTC_IRQ(MTU1_AB, 154), + INTC_IRQ(MTU1_VU, 155), INTC_IRQ(MTU1_VU, 156), + INTC_IRQ(MTU2_AB, 157), INTC_IRQ(MTU2_AB, 158), + INTC_IRQ(MTU2_VU, 159), INTC_IRQ(MTU2_VU, 160), + INTC_IRQ(MTU3_ABCD, 161), INTC_IRQ(MTU3_ABCD, 162), + INTC_IRQ(MTU3_ABCD, 163), INTC_IRQ(MTU3_ABCD, 164), INTC_IRQ(MTU2_TCI3V, 165), - INTC_IRQ(MTU2_TGI4A, 166), INTC_IRQ(MTU2_TGI4B, 167), - INTC_IRQ(MTU2_TGI4C, 168), INTC_IRQ(MTU2_TGI4D, 169), + INTC_IRQ(MTU4_ABCD, 166), INTC_IRQ(MTU4_ABCD, 167), + INTC_IRQ(MTU4_ABCD, 168), INTC_IRQ(MTU4_ABCD, 169), INTC_IRQ(MTU2_TCI4V, 170), INTC_IRQ(ADC_ADI, 171), - INTC_IRQ(IIC30_STPI, 172), INTC_IRQ(IIC30_NAKI, 173), - INTC_IRQ(IIC30_RXI, 174), INTC_IRQ(IIC30_TXI, 175), - INTC_IRQ(IIC30_TEI, 176), - INTC_IRQ(IIC31_STPI, 177), INTC_IRQ(IIC31_NAKI, 178), - INTC_IRQ(IIC31_RXI, 179), INTC_IRQ(IIC31_TXI, 180), - INTC_IRQ(IIC31_TEI, 181), - INTC_IRQ(IIC32_STPI, 182), INTC_IRQ(IIC32_NAKI, 183), - INTC_IRQ(IIC32_RXI, 184), INTC_IRQ(IIC32_TXI, 185), - INTC_IRQ(IIC32_TEI, 186), - INTC_IRQ(IIC33_STPI, 187), INTC_IRQ(IIC33_NAKI, 188), - INTC_IRQ(IIC33_RXI, 189), INTC_IRQ(IIC33_TXI, 190), - INTC_IRQ(IIC33_TEI, 191), - INTC_IRQ(SCIF0_BRI, 192), INTC_IRQ(SCIF0_ERI, 193), - INTC_IRQ(SCIF0_RXI, 194), INTC_IRQ(SCIF0_TXI, 195), - INTC_IRQ(SCIF1_BRI, 196), INTC_IRQ(SCIF1_ERI, 197), - INTC_IRQ(SCIF1_RXI, 198), INTC_IRQ(SCIF1_TXI, 199), - INTC_IRQ(SCIF2_BRI, 200), INTC_IRQ(SCIF2_ERI, 201), - INTC_IRQ(SCIF2_RXI, 202), INTC_IRQ(SCIF2_TXI, 203), - INTC_IRQ(SCIF3_BRI, 204), INTC_IRQ(SCIF3_ERI, 205), - INTC_IRQ(SCIF3_RXI, 206), INTC_IRQ(SCIF3_TXI, 207), - INTC_IRQ(SSU0_SSERI, 208), INTC_IRQ(SSU0_SSRXI, 209), - INTC_IRQ(SSU0_SSTXI, 210), - INTC_IRQ(SSU1_SSERI, 211), INTC_IRQ(SSU1_SSRXI, 212), - INTC_IRQ(SSU1_SSTXI, 213), + INTC_IRQ(IIC30, 172), INTC_IRQ(IIC30, 173), + INTC_IRQ(IIC30, 174), INTC_IRQ(IIC30, 175), + INTC_IRQ(IIC30, 176), + INTC_IRQ(IIC31, 177), INTC_IRQ(IIC31, 178), + INTC_IRQ(IIC31, 179), INTC_IRQ(IIC31, 180), + INTC_IRQ(IIC31, 181), + INTC_IRQ(IIC32, 182), INTC_IRQ(IIC32, 183), + INTC_IRQ(IIC32, 184), INTC_IRQ(IIC32, 185), + INTC_IRQ(IIC32, 186), + INTC_IRQ(IIC33, 187), INTC_IRQ(IIC33, 188), + INTC_IRQ(IIC33, 189), INTC_IRQ(IIC33, 190), + INTC_IRQ(IIC33, 191), + INTC_IRQ(SCIF0, 192), INTC_IRQ(SCIF0, 193), + INTC_IRQ(SCIF0, 194), INTC_IRQ(SCIF0, 195), + INTC_IRQ(SCIF1, 196), INTC_IRQ(SCIF1, 197), + INTC_IRQ(SCIF1, 198), INTC_IRQ(SCIF1, 199), + INTC_IRQ(SCIF2, 200), INTC_IRQ(SCIF2, 201), + INTC_IRQ(SCIF2, 202), INTC_IRQ(SCIF2, 203), + INTC_IRQ(SCIF3, 204), INTC_IRQ(SCIF3, 205), + INTC_IRQ(SCIF3, 206), INTC_IRQ(SCIF3, 207), + INTC_IRQ(SSU0, 208), INTC_IRQ(SSU0, 209), + INTC_IRQ(SSU0, 210), + INTC_IRQ(SSU1, 211), INTC_IRQ(SSU1, 212), + INTC_IRQ(SSU1, 213), INTC_IRQ(SSI0_SSII, 214), INTC_IRQ(SSI1_SSII, 215), INTC_IRQ(SSI2_SSII, 216), INTC_IRQ(SSI3_SSII, 217), - INTC_IRQ(FLCTL_FLSTEI, 224), INTC_IRQ(FLCTL_FLTENDI, 225), - INTC_IRQ(FLCTL_FLTREQ0I, 226), INTC_IRQ(FLCTL_FLTREQ1I, 227), - INTC_IRQ(RTC_ARM, 231), INTC_IRQ(RTC_PRD, 232), - INTC_IRQ(RTC_CUP, 233), - INTC_IRQ(RCAN0_ERS, 234), INTC_IRQ(RCAN0_OVR, 235), - INTC_IRQ(RCAN0_RM0, 236), INTC_IRQ(RCAN0_RM1, 237), - INTC_IRQ(RCAN0_SLE, 238), - INTC_IRQ(RCAN1_ERS, 239), INTC_IRQ(RCAN1_OVR, 240), - INTC_IRQ(RCAN1_RM0, 241), INTC_IRQ(RCAN1_RM1, 242), - INTC_IRQ(RCAN1_SLE, 243), + INTC_IRQ(FLCTL, 224), INTC_IRQ(FLCTL, 225), + INTC_IRQ(FLCTL, 226), INTC_IRQ(FLCTL, 227), + INTC_IRQ(RTC, 231), INTC_IRQ(RTC, 232), + INTC_IRQ(RTC, 233), + INTC_IRQ(RCAN0, 234), INTC_IRQ(RCAN0, 235), + INTC_IRQ(RCAN0, 236), INTC_IRQ(RCAN0, 237), + INTC_IRQ(RCAN0, 238), + INTC_IRQ(RCAN1, 239), INTC_IRQ(RCAN1, 240), + INTC_IRQ(RCAN1, 241), INTC_IRQ(RCAN1, 242), + INTC_IRQ(RCAN1, 243), /* SH7263-specific trash */ #ifdef CONFIG_CPU_SUBTYPE_SH7263 - INTC_IRQ(ROMDEC_ISY, 218), INTC_IRQ(ROMDEC_IERR, 219), - INTC_IRQ(ROMDEC_IARG, 220), INTC_IRQ(ROMDEC_ISEC, 221), - INTC_IRQ(ROMDEC_IBUF, 222), INTC_IRQ(ROMDEC_IREADY, 223), + INTC_IRQ(ROMDEC, 218), INTC_IRQ(ROMDEC, 219), + INTC_IRQ(ROMDEC, 220), INTC_IRQ(ROMDEC, 221), + INTC_IRQ(ROMDEC, 222), INTC_IRQ(ROMDEC, 223), - INTC_IRQ(SDHI3, 228), INTC_IRQ(SDHI0, 229), INTC_IRQ(SDHI1, 230), + INTC_IRQ(SDHI, 228), INTC_IRQ(SDHI, 229), + INTC_IRQ(SDHI, 230), - INTC_IRQ(SRC_OVF, 244), INTC_IRQ(SRC_ODFI, 245), - INTC_IRQ(SRC_IDEI, 246), + INTC_IRQ(SRC, 244), INTC_IRQ(SRC, 245), + INTC_IRQ(SRC, 246), INTC_IRQ(IEBI, 247), #endif @@ -154,50 +132,6 @@ static struct intc_vect vectors[] __initdata = { static struct intc_group groups[] __initdata = { INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7), - INTC_GROUP(DMAC0, DMAC0_DEI, DMAC0_HEI), - INTC_GROUP(DMAC1, DMAC1_DEI, DMAC1_HEI), - INTC_GROUP(DMAC2, DMAC2_DEI, DMAC2_HEI), - INTC_GROUP(DMAC3, DMAC3_DEI, DMAC3_HEI), - INTC_GROUP(DMAC4, DMAC4_DEI, DMAC4_HEI), - INTC_GROUP(DMAC5, DMAC5_DEI, DMAC5_HEI), - INTC_GROUP(DMAC6, DMAC6_DEI, DMAC6_HEI), - INTC_GROUP(DMAC7, DMAC7_DEI, DMAC7_HEI), - INTC_GROUP(MTU0_ABCD, MTU2_TGI0A, MTU2_TGI0B, MTU2_TGI0C, MTU2_TGI0D), - INTC_GROUP(MTU0_VEF, MTU2_TCI0V, MTU2_TGI0E, MTU2_TGI0F), - INTC_GROUP(MTU1_AB, MTU2_TGI1A, MTU2_TGI1B), - INTC_GROUP(MTU1_VU, MTU2_TCI1V, MTU2_TCI1U), - INTC_GROUP(MTU2_AB, MTU2_TGI2A, MTU2_TGI2B), - INTC_GROUP(MTU2_VU, MTU2_TCI2V, MTU2_TCI2U), - INTC_GROUP(MTU3_ABCD, MTU2_TGI3A, MTU2_TGI3B, MTU2_TGI3C, MTU2_TGI3D), - INTC_GROUP(MTU4_ABCD, MTU2_TGI4A, MTU2_TGI4B, MTU2_TGI4C, MTU2_TGI4D), - INTC_GROUP(IIC30, IIC30_STPI, IIC30_NAKI, IIC30_RXI, IIC30_TXI, - IIC30_TEI), - INTC_GROUP(IIC31, IIC31_STPI, IIC31_NAKI, IIC31_RXI, IIC31_TXI, - IIC31_TEI), - INTC_GROUP(IIC32, IIC32_STPI, IIC32_NAKI, IIC32_RXI, IIC32_TXI, - IIC32_TEI), - INTC_GROUP(IIC33, IIC33_STPI, IIC33_NAKI, IIC33_RXI, IIC33_TXI, - IIC33_TEI), - INTC_GROUP(SCIF0, SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI), - INTC_GROUP(SCIF1, SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI), - INTC_GROUP(SCIF2, SCIF2_BRI, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI), - INTC_GROUP(SCIF3, SCIF3_BRI, SCIF3_ERI, SCIF3_RXI, SCIF3_TXI), - INTC_GROUP(SSU0, SSU0_SSERI, SSU0_SSRXI, SSU0_SSTXI), - INTC_GROUP(SSU1, SSU1_SSERI, SSU1_SSRXI, SSU1_SSTXI), - INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, - FLCTL_FLTREQ1I), - INTC_GROUP(RTC, RTC_ARM, RTC_PRD, RTC_CUP), - INTC_GROUP(RCAN0, RCAN0_ERS, RCAN0_OVR, RCAN0_RM0, RCAN0_RM1, - RCAN0_SLE), - INTC_GROUP(RCAN1, RCAN1_ERS, RCAN1_OVR, RCAN1_RM0, RCAN1_RM1, - RCAN1_SLE), - -#ifdef CONFIG_CPU_SUBTYPE_SH7263 - INTC_GROUP(ROMDEC, ROMDEC_ISY, ROMDEC_IERR, ROMDEC_IARG, - ROMDEC_ISEC, ROMDEC_IBUF, ROMDEC_IREADY), - INTC_GROUP(SDHI, SDHI3, SDHI0, SDHI1), - INTC_GROUP(SRC, SRC_OVF, SRC_ODFI, SRC_IDEI), -#endif }; static struct intc_prio_reg prio_registers[] __initdata = { @@ -242,22 +176,22 @@ static struct plat_sci_port sci_platform_data[] = { .mapbase = 0xfffe8000, .flags = UPF_BOOT_AUTOCONF, .type = PORT_SCIF, - .irqs = { 193, 194, 195, 192 }, + .irqs = { 192, 192, 192, 192 }, }, { .mapbase = 0xfffe8800, .flags = UPF_BOOT_AUTOCONF, .type = PORT_SCIF, - .irqs = { 197, 198, 199, 196 }, + .irqs = { 196, 196, 196, 196 }, }, { .mapbase = 0xfffe9000, .flags = UPF_BOOT_AUTOCONF, .type = PORT_SCIF, - .irqs = { 201, 202, 203, 200 }, + .irqs = { 200, 200, 200, 200 }, }, { .mapbase = 0xfffe9800, .flags = UPF_BOOT_AUTOCONF, .type = PORT_SCIF, - .irqs = { 205, 206, 207, 204 }, + .irqs = { 204, 204, 204, 204 }, }, { .flags = 0, } @@ -278,17 +212,7 @@ static struct resource rtc_resources[] = { .flags = IORESOURCE_IO, }, [1] = { - /* Period IRQ */ - .start = 232, - .flags = IORESOURCE_IRQ, - }, - [2] = { - /* Carry IRQ */ - .start = 233, - .flags = IORESOURCE_IRQ, - }, - [3] = { - /* Alarm IRQ */ + /* Shared Period/Carry/Alarm IRQ */ .start = 231, .flags = IORESOURCE_IRQ, }, diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7206.c b/arch/sh/kernel/cpu/sh2a/setup-sh7206.c index e6d4ec445dd..c46a8355726 100644 --- a/arch/sh/kernel/cpu/sh2a/setup-sh7206.c +++ b/arch/sh/kernel/cpu/sh2a/setup-sh7206.c @@ -2,6 +2,7 @@ * SH7206 Setup * * Copyright (C) 2006 Yoshinori Sato + * Copyright (C) 2009 Paul Mundt * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive @@ -19,34 +20,23 @@ enum { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7, ADC_ADI0, ADC_ADI1, - DMAC0_DEI, DMAC0_HEI, DMAC1_DEI, DMAC1_HEI, - DMAC2_DEI, DMAC2_HEI, DMAC3_DEI, DMAC3_HEI, - DMAC4_DEI, DMAC4_HEI, DMAC5_DEI, DMAC5_HEI, - DMAC6_DEI, DMAC6_HEI, DMAC7_DEI, DMAC7_HEI, + + DMAC0, DMAC1, DMAC2, DMAC3, DMAC4, DMAC5, DMAC6, DMAC7, + + MTU0_ABCD, MTU0_VEF, MTU1_AB, MTU1_VU, MTU2_AB, MTU2_VU, + MTU3_ABCD, MTU4_ABCD, MTU5, POE2_12, MTU3S_ABCD, MTU4S_ABCD, MTU5S, + IIC3, + CMT0, CMT1, BSC, WDT, - MTU2_TGI0A, MTU2_TGI0B, MTU2_TGI0C, MTU2_TGI0D, - MTU2_TCI0V, MTU2_TGI0E, MTU2_TGI0F, - MTU2_TGI1A, MTU2_TGI1B, MTU2_TCI1V, MTU2_TCI1U, - MTU2_TGI2A, MTU2_TGI2B, MTU2_TCI2V, MTU2_TCI2U, - MTU2_TGI3A, MTU2_TGI3B, MTU2_TGI3C, MTU2_TGI3D, MTU2_TCI3V, - MTU2_TGI4A, MTU2_TGI4B, MTU2_TGI4C, MTU2_TGI4D, MTU2_TCI4V, - MTU2_TGI5U, MTU2_TGI5V, MTU2_TGI5W, - POE2_OEI1, POE2_OEI2, - MTU2S_TGI3A, MTU2S_TGI3B, MTU2S_TGI3C, MTU2S_TGI3D, MTU2S_TCI3V, - MTU2S_TGI4A, MTU2S_TGI4B, MTU2S_TGI4C, MTU2S_TGI4D, MTU2S_TCI4V, - MTU2S_TGI5U, MTU2S_TGI5V, MTU2S_TGI5W, + + MTU2_TCI3V, MTU2_TCI4V, MTU2S_TCI3V, MTU2S_TCI4V, + POE2_OEI3, - IIC3_STPI, IIC3_NAKI, IIC3_RXI, IIC3_TXI, IIC3_TEI, - SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI, - SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI, - SCIF2_BRI, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI, - SCIF3_BRI, SCIF3_ERI, SCIF3_RXI, SCIF3_TXI, + + SCIF0, SCIF1, SCIF2, SCIF3, /* interrupt groups */ - PINT, DMAC0, DMAC1, DMAC2, DMAC3, DMAC4, DMAC5, DMAC6, DMAC7, - MTU0_ABCD, MTU0_VEF, MTU1_AB, MTU1_VU, MTU2_AB, MTU2_VU, - MTU3_ABCD, MTU4_ABCD, MTU5, POE2_12, MTU3S_ABCD, MTU4S_ABCD, MTU5S, - IIC3, SCIF0, SCIF1, SCIF2, SCIF3, + PINT, }; static struct intc_vect vectors[] __initdata = { @@ -59,86 +49,58 @@ static struct intc_vect vectors[] __initdata = { INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85), INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87), INTC_IRQ(ADC_ADI0, 92), INTC_IRQ(ADC_ADI1, 96), - INTC_IRQ(DMAC0_DEI, 108), INTC_IRQ(DMAC0_HEI, 109), - INTC_IRQ(DMAC1_DEI, 112), INTC_IRQ(DMAC1_HEI, 113), - INTC_IRQ(DMAC2_DEI, 116), INTC_IRQ(DMAC2_HEI, 117), - INTC_IRQ(DMAC3_DEI, 120), INTC_IRQ(DMAC3_HEI, 121), - INTC_IRQ(DMAC4_DEI, 124), INTC_IRQ(DMAC4_HEI, 125), - INTC_IRQ(DMAC5_DEI, 128), INTC_IRQ(DMAC5_HEI, 129), - INTC_IRQ(DMAC6_DEI, 132), INTC_IRQ(DMAC6_HEI, 133), - INTC_IRQ(DMAC7_DEI, 136), INTC_IRQ(DMAC7_HEI, 137), + INTC_IRQ(DMAC0, 108), INTC_IRQ(DMAC0, 109), + INTC_IRQ(DMAC1, 112), INTC_IRQ(DMAC1, 113), + INTC_IRQ(DMAC2, 116), INTC_IRQ(DMAC2, 117), + INTC_IRQ(DMAC3, 120), INTC_IRQ(DMAC3, 121), + INTC_IRQ(DMAC4, 124), INTC_IRQ(DMAC4, 125), + INTC_IRQ(DMAC5, 128), INTC_IRQ(DMAC5, 129), + INTC_IRQ(DMAC6, 132), INTC_IRQ(DMAC6, 133), + INTC_IRQ(DMAC7, 136), INTC_IRQ(DMAC7, 137), INTC_IRQ(CMT0, 140), INTC_IRQ(CMT1, 144), INTC_IRQ(BSC, 148), INTC_IRQ(WDT, 152), - INTC_IRQ(MTU2_TGI0A, 156), INTC_IRQ(MTU2_TGI0B, 157), - INTC_IRQ(MTU2_TGI0C, 158), INTC_IRQ(MTU2_TGI0D, 159), - INTC_IRQ(MTU2_TCI0V, 160), - INTC_IRQ(MTU2_TGI0E, 161), INTC_IRQ(MTU2_TGI0F, 162), - INTC_IRQ(MTU2_TGI1A, 164), INTC_IRQ(MTU2_TGI1B, 165), - INTC_IRQ(MTU2_TCI1V, 168), INTC_IRQ(MTU2_TCI1U, 169), - INTC_IRQ(MTU2_TGI2A, 172), INTC_IRQ(MTU2_TGI2B, 173), - INTC_IRQ(MTU2_TCI2V, 176), INTC_IRQ(MTU2_TCI2U, 177), - INTC_IRQ(MTU2_TGI3A, 180), INTC_IRQ(MTU2_TGI3B, 181), - INTC_IRQ(MTU2_TGI3C, 182), INTC_IRQ(MTU2_TGI3D, 183), + INTC_IRQ(MTU0_ABCD, 156), INTC_IRQ(MTU0_ABCD, 157), + INTC_IRQ(MTU0_ABCD, 158), INTC_IRQ(MTU0_ABCD, 159), + INTC_IRQ(MTU0_VEF, 160), INTC_IRQ(MTU0_VEF, 161), + INTC_IRQ(MTU0_VEF, 162), + INTC_IRQ(MTU1_AB, 164), INTC_IRQ(MTU1_AB, 165), + INTC_IRQ(MTU1_VU, 168), INTC_IRQ(MTU1_VU, 169), + INTC_IRQ(MTU2_AB, 172), INTC_IRQ(MTU2_AB, 173), + INTC_IRQ(MTU2_VU, 176), INTC_IRQ(MTU2_VU, 177), + INTC_IRQ(MTU3_ABCD, 180), INTC_IRQ(MTU3_ABCD, 181), + INTC_IRQ(MTU3_ABCD, 182), INTC_IRQ(MTU3_ABCD, 183), INTC_IRQ(MTU2_TCI3V, 184), - INTC_IRQ(MTU2_TGI4A, 188), INTC_IRQ(MTU2_TGI4B, 189), - INTC_IRQ(MTU2_TGI4C, 190), INTC_IRQ(MTU2_TGI4D, 191), + INTC_IRQ(MTU4_ABCD, 188), INTC_IRQ(MTU4_ABCD, 189), + INTC_IRQ(MTU4_ABCD, 190), INTC_IRQ(MTU4_ABCD, 191), INTC_IRQ(MTU2_TCI4V, 192), - INTC_IRQ(MTU2_TGI5U, 196), INTC_IRQ(MTU2_TGI5V, 197), - INTC_IRQ(MTU2_TGI5W, 198), - INTC_IRQ(POE2_OEI1, 200), INTC_IRQ(POE2_OEI2, 201), - INTC_IRQ(MTU2S_TGI3A, 204), INTC_IRQ(MTU2S_TGI3B, 205), - INTC_IRQ(MTU2S_TGI3C, 206), INTC_IRQ(MTU2S_TGI3D, 207), + INTC_IRQ(MTU5, 196), INTC_IRQ(MTU5, 197), + INTC_IRQ(MTU5, 198), + INTC_IRQ(POE2_12, 200), INTC_IRQ(POE2_12, 201), + INTC_IRQ(MTU3S_ABCD, 204), INTC_IRQ(MTU3S_ABCD, 205), + INTC_IRQ(MTU3S_ABCD, 206), INTC_IRQ(MTU3S_ABCD, 207), INTC_IRQ(MTU2S_TCI3V, 208), - INTC_IRQ(MTU2S_TGI4A, 212), INTC_IRQ(MTU2S_TGI4B, 213), - INTC_IRQ(MTU2S_TGI4C, 214), INTC_IRQ(MTU2S_TGI4D, 215), + INTC_IRQ(MTU4S_ABCD, 212), INTC_IRQ(MTU4S_ABCD, 213), + INTC_IRQ(MTU4S_ABCD, 214), INTC_IRQ(MTU4S_ABCD, 215), INTC_IRQ(MTU2S_TCI4V, 216), - INTC_IRQ(MTU2S_TGI5U, 220), INTC_IRQ(MTU2S_TGI5V, 221), - INTC_IRQ(MTU2S_TGI5W, 222), + INTC_IRQ(MTU5S, 220), INTC_IRQ(MTU5S, 221), + INTC_IRQ(MTU5S, 222), INTC_IRQ(POE2_OEI3, 224), - INTC_IRQ(IIC3_STPI, 228), INTC_IRQ(IIC3_NAKI, 229), - INTC_IRQ(IIC3_RXI, 230), INTC_IRQ(IIC3_TXI, 231), - INTC_IRQ(IIC3_TEI, 232), - INTC_IRQ(SCIF0_BRI, 240), INTC_IRQ(SCIF0_ERI, 241), - INTC_IRQ(SCIF0_RXI, 242), INTC_IRQ(SCIF0_TXI, 243), - INTC_IRQ(SCIF1_BRI, 244), INTC_IRQ(SCIF1_ERI, 245), - INTC_IRQ(SCIF1_RXI, 246), INTC_IRQ(SCIF1_TXI, 247), - INTC_IRQ(SCIF2_BRI, 248), INTC_IRQ(SCIF2_ERI, 249), - INTC_IRQ(SCIF2_RXI, 250), INTC_IRQ(SCIF2_TXI, 251), - INTC_IRQ(SCIF3_BRI, 252), INTC_IRQ(SCIF3_ERI, 253), - INTC_IRQ(SCIF3_RXI, 254), INTC_IRQ(SCIF3_TXI, 255), + INTC_IRQ(IIC3, 228), INTC_IRQ(IIC3, 229), + INTC_IRQ(IIC3, 230), INTC_IRQ(IIC3, 231), + INTC_IRQ(IIC3, 232), + INTC_IRQ(SCIF0, 240), INTC_IRQ(SCIF0, 241), + INTC_IRQ(SCIF0, 242), INTC_IRQ(SCIF0, 243), + INTC_IRQ(SCIF1, 244), INTC_IRQ(SCIF1, 245), + INTC_IRQ(SCIF1, 246), INTC_IRQ(SCIF1, 247), + INTC_IRQ(SCIF2, 248), INTC_IRQ(SCIF2, 249), + INTC_IRQ(SCIF2, 250), INTC_IRQ(SCIF2, 251), + INTC_IRQ(SCIF3, 252), INTC_IRQ(SCIF3, 253), + INTC_IRQ(SCIF3, 254), INTC_IRQ(SCIF3, 255), }; static struct intc_group groups[] __initdata = { INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7), - INTC_GROUP(DMAC0, DMAC0_DEI, DMAC0_HEI), - INTC_GROUP(DMAC1, DMAC1_DEI, DMAC1_HEI), - INTC_GROUP(DMAC2, DMAC2_DEI, DMAC2_HEI), - INTC_GROUP(DMAC3, DMAC3_DEI, DMAC3_HEI), - INTC_GROUP(DMAC4, DMAC4_DEI, DMAC4_HEI), - INTC_GROUP(DMAC5, DMAC5_DEI, DMAC5_HEI), - INTC_GROUP(DMAC6, DMAC6_DEI, DMAC6_HEI), - INTC_GROUP(DMAC7, DMAC7_DEI, DMAC7_HEI), - INTC_GROUP(MTU0_ABCD, MTU2_TGI0A, MTU2_TGI0B, MTU2_TGI0C, MTU2_TGI0D), - INTC_GROUP(MTU0_VEF, MTU2_TCI0V, MTU2_TGI0E, MTU2_TGI0F), - INTC_GROUP(MTU1_AB, MTU2_TGI1A, MTU2_TGI1B), - INTC_GROUP(MTU1_VU, MTU2_TCI1V, MTU2_TCI1U), - INTC_GROUP(MTU2_AB, MTU2_TGI2A, MTU2_TGI2B), - INTC_GROUP(MTU2_VU, MTU2_TCI2V, MTU2_TCI2U), - INTC_GROUP(MTU3_ABCD, MTU2_TGI3A, MTU2_TGI3B, MTU2_TGI3C, MTU2_TGI3D), - INTC_GROUP(MTU4_ABCD, MTU2_TGI4A, MTU2_TGI4B, MTU2_TGI4C, MTU2_TGI4D), - INTC_GROUP(MTU5, MTU2_TGI5U, MTU2_TGI5V, MTU2_TGI5W), - INTC_GROUP(POE2_12, POE2_OEI1, POE2_OEI2), - INTC_GROUP(MTU3S_ABCD, MTU2S_TGI3A, MTU2S_TGI3B, - MTU2S_TGI3C, MTU2S_TGI3D), - INTC_GROUP(MTU4S_ABCD, MTU2S_TGI4A, MTU2S_TGI4B, - MTU2S_TGI4C, MTU2S_TGI4D), - INTC_GROUP(MTU5S, MTU2S_TGI5U, MTU2S_TGI5V, MTU2S_TGI5W), - INTC_GROUP(IIC3, IIC3_STPI, IIC3_NAKI, IIC3_RXI, IIC3_TXI, IIC3_TEI), - INTC_GROUP(SCIF0, SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI), - INTC_GROUP(SCIF1, SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI), - INTC_GROUP(SCIF2, SCIF2_BRI, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI), - INTC_GROUP(SCIF3, SCIF3_BRI, SCIF3_ERI, SCIF3_RXI, SCIF3_TXI), }; static struct intc_prio_reg prio_registers[] __initdata = { @@ -174,22 +136,22 @@ static struct plat_sci_port sci_platform_data[] = { .mapbase = 0xfffe8000, .flags = UPF_BOOT_AUTOCONF, .type = PORT_SCIF, - .irqs = { 241, 242, 243, 240 }, + .irqs = { 240, 240, 240, 240 }, }, { .mapbase = 0xfffe8800, .flags = UPF_BOOT_AUTOCONF, .type = PORT_SCIF, - .irqs = { 245, 246, 247, 244 }, + .irqs = { 244, 244, 244, 244 }, }, { .mapbase = 0xfffe9000, .flags = UPF_BOOT_AUTOCONF, .type = PORT_SCIF, - .irqs = { 249, 250, 251, 248 }, + .irqs = { 248, 248, 248, 248 }, }, { .mapbase = 0xfffe9800, .flags = UPF_BOOT_AUTOCONF, .type = PORT_SCIF, - .irqs = { 253, 254, 255, 252 }, + .irqs = { 252, 252, 252, 252 }, }, { .flags = 0, } |