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authorPaul Mundt <lethal@linux-sh.org>2008-04-09 17:58:22 +0900
committerPaul Mundt <lethal@linux-sh.org>2008-04-18 09:50:07 -0700
commit440fc172ae333c52c458401fe059afcc6e91eebf (patch)
treebc25cfb81ec590ff5d8eb8facd84206248f93d2c /arch/sh/kernel
parente5a4c65bef19366112ba002bc06d87450f02ad74 (diff)
sh: Fix up L2 cache probe.
SH7723 is the first hard silicon to implement the L2, and unsurprisingly, does the precise inverse of what the specification alleges. XOR the URAM/L2 size bits to get back in line with the existing parsing logic. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/kernel')
-rw-r--r--arch/sh/kernel/cpu/sh4/probe.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/sh/kernel/cpu/sh4/probe.c b/arch/sh/kernel/cpu/sh4/probe.c
index 6ea87af7247..ebceb0dadff 100644
--- a/arch/sh/kernel/cpu/sh4/probe.c
+++ b/arch/sh/kernel/cpu/sh4/probe.c
@@ -220,6 +220,12 @@ int __init detect_cpu_and_cache_system(void)
* SH-4A's have an optional PIPT L2.
*/
if (boot_cpu_data.flags & CPU_HAS_L2_CACHE) {
+ /* Bug if we can't decode the L2 info */
+ BUG_ON(!(cvr & 0xf));
+
+ /* Silicon and specifications have clearly never met.. */
+ cvr ^= 0xf;
+
/*
* Size calculation is much more sensible
* than it is for the L1.