sh: Fixup cpu_data references for the non-boot CPUs.

There are a lot of bogus cpu_data-> references that only end up working
for the boot CPU, convert these to current_cpu_data to fixup SMP.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>

7 files changed, 54 insertions, 53 deletions

diff --git a/arch/sh/mm/cache-debugfs.c b/arch/sh/mm/cache-debugfs.c
index 909dcfa8c8c..de6d2c9aa47 100644
--- a/arch/sh/mm/cache-debugfs.c
+++ b/arch/sh/mm/cache-debugfs.c
@@ -46,10 +46,10 @@ static int cache_seq_show(struct seq_file *file, void *iter)
 
 	if (cache_type == CACHE_TYPE_DCACHE) {
 		base = CACHE_OC_ADDRESS_ARRAY;
-		cache = &cpu_data->dcache;
+		cache = &current_cpu_data.dcache;
 	} else {
 		base = CACHE_IC_ADDRESS_ARRAY;
-		cache = &cpu_data->icache;
+		cache = &current_cpu_data.icache;
 	}
 
 	/*
diff --git a/arch/sh/mm/cache-sh3.c b/arch/sh/mm/cache-sh3.c
index 838731fc608..6d1dbec08ad 100644
--- a/arch/sh/mm/cache-sh3.c
+++ b/arch/sh/mm/cache-sh3.c
@@ -44,11 +44,11 @@ void __flush_wback_region(void *start, int size)
 
 	for (v = begin; v < end; v+=L1_CACHE_BYTES) {
 		unsigned long addrstart = CACHE_OC_ADDRESS_ARRAY;
-		for (j = 0; j < cpu_data->dcache.ways; j++) {
+		for (j = 0; j < current_cpu_data.dcache.ways; j++) {
 			unsigned long data, addr, p;
 
 			p = __pa(v);
-			addr = addrstart | (v & cpu_data->dcache.entry_mask);
+			addr = addrstart | (v & current_cpu_data.dcache.entry_mask);
 			local_irq_save(flags);
 			data = ctrl_inl(addr);
 
@@ -60,7 +60,7 @@ void __flush_wback_region(void *start, int size)
 				break;
 			}
 			local_irq_restore(flags);
-			addrstart += cpu_data->dcache.way_incr;
+			addrstart += current_cpu_data.dcache.way_incr;
 		}
 	}
 }
@@ -85,7 +85,7 @@ void __flush_purge_region(void *start, int size)
 
 		data = (v & 0xfffffc00); /* _Virtual_ address, ~U, ~V */
 		addr = CACHE_OC_ADDRESS_ARRAY |
-			(v & cpu_data->dcache.entry_mask) | SH_CACHE_ASSOC;
+			(v & current_cpu_data.dcache.entry_mask) | SH_CACHE_ASSOC;
 		ctrl_outl(data, addr);
 	}
 }
diff --git a/arch/sh/mm/cache-sh4.c b/arch/sh/mm/cache-sh4.c
index 72bb4877333..e0cd4b7f4ae 100644
--- a/arch/sh/mm/cache-sh4.c
+++ b/arch/sh/mm/cache-sh4.c
@@ -54,21 +54,21 @@ static void __init emit_cache_params(void)
 		ctrl_inl(CCN_CVR),
 		ctrl_inl(CCN_PRR));
 	printk("I-cache : n_ways=%d n_sets=%d way_incr=%d\n",
-		cpu_data->icache.ways,
-		cpu_data->icache.sets,
-		cpu_data->icache.way_incr);
+		current_cpu_data.icache.ways,
+		current_cpu_data.icache.sets,
+		current_cpu_data.icache.way_incr);
 	printk("I-cache : entry_mask=0x%08x alias_mask=0x%08x n_aliases=%d\n",
-		cpu_data->icache.entry_mask,
-		cpu_data->icache.alias_mask,
-		cpu_data->icache.n_aliases);
+		current_cpu_data.icache.entry_mask,
+		current_cpu_data.icache.alias_mask,
+		current_cpu_data.icache.n_aliases);
 	printk("D-cache : n_ways=%d n_sets=%d way_incr=%d\n",
-		cpu_data->dcache.ways,
-		cpu_data->dcache.sets,
-		cpu_data->dcache.way_incr);
+		current_cpu_data.dcache.ways,
+		current_cpu_data.dcache.sets,
+		current_cpu_data.dcache.way_incr);
 	printk("D-cache : entry_mask=0x%08x alias_mask=0x%08x n_aliases=%d\n",
-		cpu_data->dcache.entry_mask,
-		cpu_data->dcache.alias_mask,
-		cpu_data->dcache.n_aliases);
+		current_cpu_data.dcache.entry_mask,
+		current_cpu_data.dcache.alias_mask,
+		current_cpu_data.dcache.n_aliases);
 
 	if (!__flush_dcache_segment_fn)
 		panic("unknown number of cache ways\n");
@@ -87,10 +87,10 @@ void __init p3_cache_init(void)
 {
 	int i;
 
-	compute_alias(&cpu_data->icache);
-	compute_alias(&cpu_data->dcache);
+	compute_alias(&current_cpu_data.icache);
+	compute_alias(&current_cpu_data.dcache);
 
-	switch (cpu_data->dcache.ways) {
+	switch (current_cpu_data.dcache.ways) {
 	case 1:
 		__flush_dcache_segment_fn = __flush_dcache_segment_1way;
 		break;
@@ -110,7 +110,7 @@ void __init p3_cache_init(void)
 	if (ioremap_page_range(P3SEG, P3SEG + (PAGE_SIZE * 4), 0, PAGE_KERNEL))
 		panic("%s failed.", __FUNCTION__);
 
-	for (i = 0; i < cpu_data->dcache.n_aliases; i++)
+	for (i = 0; i < current_cpu_data.dcache.n_aliases; i++)
 		mutex_init(&p3map_mutex[i]);
 }
 
@@ -200,13 +200,14 @@ void flush_cache_sigtramp(unsigned long addr)
 		     : /* no output */
 		     : "m" (__m(v)));
 
-	index = CACHE_IC_ADDRESS_ARRAY | (v & cpu_data->icache.entry_mask);
+	index = CACHE_IC_ADDRESS_ARRAY |
+			(v & current_cpu_data.icache.entry_mask);
 
 	local_irq_save(flags);
 	jump_to_P2();
 
-	for (i = 0; i < cpu_data->icache.ways;
-	     i++, index += cpu_data->icache.way_incr)
+	for (i = 0; i < current_cpu_data.icache.ways;
+	     i++, index += current_cpu_data.icache.way_incr)
 		ctrl_outl(0, index);	/* Clear out Valid-bit */
 
 	back_to_P1();
@@ -223,7 +224,7 @@ static inline void flush_cache_4096(unsigned long start,
 	 * All types of SH-4 require PC to be in P2 to operate on the I-cache.
 	 * Some types of SH-4 require PC to be in P2 to operate on the D-cache.
 	 */
-	if ((cpu_data->flags & CPU_HAS_P2_FLUSH_BUG) ||
+	if ((current_cpu_data.flags & CPU_HAS_P2_FLUSH_BUG) ||
 	    (start < CACHE_OC_ADDRESS_ARRAY))
 		exec_offset = 0x20000000;
 
@@ -255,7 +256,7 @@ void flush_dcache_page(struct page *page)
 		int i, n;
 
 		/* Loop all the D-cache */
-		n = cpu_data->dcache.n_aliases;
+		n = current_cpu_data.dcache.n_aliases;
 		for (i = 0; i < n; i++, addr += 4096)
 			flush_cache_4096(addr, phys);
 	}
@@ -287,7 +288,7 @@ static inline void flush_icache_all(void)
 
 void flush_dcache_all(void)
 {
-	(*__flush_dcache_segment_fn)(0UL, cpu_data->dcache.way_size);
+	(*__flush_dcache_segment_fn)(0UL, current_cpu_data.dcache.way_size);
 	wmb();
 }
 
@@ -301,8 +302,8 @@ static void __flush_cache_mm(struct mm_struct *mm, unsigned long start,
 			     unsigned long end)
 {
 	unsigned long d = 0, p = start & PAGE_MASK;
-	unsigned long alias_mask = cpu_data->dcache.alias_mask;
-	unsigned long n_aliases = cpu_data->dcache.n_aliases;
+	unsigned long alias_mask = current_cpu_data.dcache.alias_mask;
+	unsigned long n_aliases = current_cpu_data.dcache.n_aliases;
 	unsigned long select_bit;
 	unsigned long all_aliases_mask;
 	unsigned long addr_offset;
@@ -389,7 +390,7 @@ void flush_cache_mm(struct mm_struct *mm)
 	 * If cache is only 4k-per-way, there are never any 'aliases'.  Since
 	 * the cache is physically tagged, the data can just be left in there.
 	 */
-	if (cpu_data->dcache.n_aliases == 0)
+	if (current_cpu_data.dcache.n_aliases == 0)
 		return;
 
 	/*
@@ -426,7 +427,7 @@ void flush_cache_page(struct vm_area_struct *vma, unsigned long address,
 	unsigned long phys = pfn << PAGE_SHIFT;
 	unsigned int alias_mask;
 
-	alias_mask = cpu_data->dcache.alias_mask;
+	alias_mask = current_cpu_data.dcache.alias_mask;
 
 	/* We only need to flush D-cache when we have alias */
 	if ((address^phys) & alias_mask) {
@@ -440,7 +441,7 @@ void flush_cache_page(struct vm_area_struct *vma, unsigned long address,
 			phys);
 	}
 
-	alias_mask = cpu_data->icache.alias_mask;
+	alias_mask = current_cpu_data.icache.alias_mask;
 	if (vma->vm_flags & VM_EXEC) {
 		/*
 		 * Evict entries from the portion of the cache from which code
@@ -472,7 +473,7 @@ void flush_cache_range(struct vm_area_struct *vma, unsigned long start,
 	 * If cache is only 4k-per-way, there are never any 'aliases'.  Since
 	 * the cache is physically tagged, the data can just be left in there.
 	 */
-	if (cpu_data->dcache.n_aliases == 0)
+	if (current_cpu_data.dcache.n_aliases == 0)
 		return;
 
 	/*
@@ -533,7 +534,7 @@ static void __flush_cache_4096(unsigned long addr, unsigned long phys,
 	unsigned long a, ea, p;
 	unsigned long temp_pc;
 
-	dcache = &cpu_data->dcache;
+	dcache = &current_cpu_data.dcache;
 	/* Write this way for better assembly. */
 	way_count = dcache->ways;
 	way_incr = dcache->way_incr;
@@ -608,7 +609,7 @@ static void __flush_dcache_segment_1way(unsigned long start,
 	base_addr = ((base_addr >> 16) << 16);
 	base_addr |= start;
 
-	dcache = &cpu_data->dcache;
+	dcache = &current_cpu_data.dcache;
 	linesz = dcache->linesz;
 	way_incr = dcache->way_incr;
 	way_size = dcache->way_size;
@@ -650,7 +651,7 @@ static void __flush_dcache_segment_2way(unsigned long start,
 	base_addr = ((base_addr >> 16) << 16);
 	base_addr |= start;
 
-	dcache = &cpu_data->dcache;
+	dcache = &current_cpu_data.dcache;
 	linesz = dcache->linesz;
 	way_incr = dcache->way_incr;
 	way_size = dcache->way_size;
@@ -709,7 +710,7 @@ static void __flush_dcache_segment_4way(unsigned long start,
 	base_addr = ((base_addr >> 16) << 16);
 	base_addr |= start;
 
-	dcache = &cpu_data->dcache;
+	dcache = &current_cpu_data.dcache;
 	linesz = dcache->linesz;
 	way_incr = dcache->way_incr;
 	way_size = dcache->way_size;
diff --git a/arch/sh/mm/cache-sh7705.c b/arch/sh/mm/cache-sh7705.c
index 2808b580d98..31f8deb7a15 100644
--- a/arch/sh/mm/cache-sh7705.c
+++ b/arch/sh/mm/cache-sh7705.c
@@ -32,9 +32,9 @@ static inline void cache_wback_all(void)
 {
 	unsigned long ways, waysize, addrstart;
 
-	ways = cpu_data->dcache.ways;
-	waysize = cpu_data->dcache.sets;
-	waysize <<= cpu_data->dcache.entry_shift;
+	ways = current_cpu_data.dcache.ways;
+	waysize = current_cpu_data.dcache.sets;
+	waysize <<= current_cpu_data.dcache.entry_shift;
 
 	addrstart = CACHE_OC_ADDRESS_ARRAY;
 
@@ -43,7 +43,7 @@ static inline void cache_wback_all(void)
 
 		for (addr = addrstart;
 		     addr < addrstart + waysize;
-		     addr += cpu_data->dcache.linesz) {
+		     addr += current_cpu_data.dcache.linesz) {
 			unsigned long data;
 			int v = SH_CACHE_UPDATED | SH_CACHE_VALID;
 
@@ -53,7 +53,7 @@ static inline void cache_wback_all(void)
 				ctrl_outl(data & ~v, addr);
 		}
 
-		addrstart += cpu_data->dcache.way_incr;
+		addrstart += current_cpu_data.dcache.way_incr;
 	} while (--ways);
 }
 
@@ -93,9 +93,9 @@ static void __flush_dcache_page(unsigned long phys)
 	local_irq_save(flags);
 	jump_to_P2();
 
-	ways = cpu_data->dcache.ways;
-	waysize = cpu_data->dcache.sets;
-	waysize <<= cpu_data->dcache.entry_shift;
+	ways = current_cpu_data.dcache.ways;
+	waysize = current_cpu_data.dcache.sets;
+	waysize <<= current_cpu_data.dcache.entry_shift;
 
 	addrstart = CACHE_OC_ADDRESS_ARRAY;
 
@@ -104,7 +104,7 @@ static void __flush_dcache_page(unsigned long phys)
 
 		for (addr = addrstart;
 		     addr < addrstart + waysize;
-		     addr += cpu_data->dcache.linesz) {
+		     addr += current_cpu_data.dcache.linesz) {
 			unsigned long data;
 
 			data = ctrl_inl(addr) & (0x1ffffC00 | SH_CACHE_VALID);
@@ -114,7 +114,7 @@ static void __flush_dcache_page(unsigned long phys)
 			}
 		}
 
-		addrstart += cpu_data->dcache.way_incr;
+		addrstart += current_cpu_data.dcache.way_incr;
 	} while (--ways);
 
 	back_to_P1();
diff --git a/arch/sh/mm/pg-sh4.c b/arch/sh/mm/pg-sh4.c
index cfc32355174..b529d809dd4 100644
--- a/arch/sh/mm/pg-sh4.c
+++ b/arch/sh/mm/pg-sh4.c
@@ -13,7 +13,7 @@
 
 extern struct mutex p3map_mutex[];
 
-#define CACHE_ALIAS (cpu_data->dcache.alias_mask)
+#define CACHE_ALIAS (current_cpu_data.dcache.alias_mask)
 
 /*
  * clear_user_page
diff --git a/arch/sh/mm/pg-sh7705.c b/arch/sh/mm/pg-sh7705.c
index b052d0fee82..887ab9d18cc 100644
--- a/arch/sh/mm/pg-sh7705.c
+++ b/arch/sh/mm/pg-sh7705.c
@@ -43,13 +43,13 @@ static inline void __flush_purge_virtual_region(void *p1, void *virt, int size)
 
 		p = __pa(p1_begin);
 
-	        ways = cpu_data->dcache.ways;
+	        ways = current_cpu_data.dcache.ways;
 		addr = CACHE_OC_ADDRESS_ARRAY;
 
 		do {
 			unsigned long data;
 
-			addr |= (v & cpu_data->dcache.entry_mask);
+			addr |= (v & current_cpu_data.dcache.entry_mask);
 
 			data = ctrl_inl(addr);
 			if ((data & CACHE_PHYSADDR_MASK) ==
@@ -58,7 +58,7 @@ static inline void __flush_purge_virtual_region(void *p1, void *virt, int size)
 				ctrl_outl(data, addr);
 			}
 
-			addr += cpu_data->dcache.way_incr;
+			addr += current_cpu_data.dcache.way_incr;
 		} while (--ways);
 
 		p1_begin += L1_CACHE_BYTES;
diff --git a/arch/sh/mm/tlb-sh3.c b/arch/sh/mm/tlb-sh3.c
index 16627069c53..598c998dba5 100644
--- a/arch/sh/mm/tlb-sh3.c
+++ b/arch/sh/mm/tlb-sh3.c
@@ -26,7 +26,7 @@ void __flush_tlb_page(unsigned long asid, unsigned long page)
 	addr = MMU_TLB_ADDRESS_ARRAY | (page & 0x1F000);
 	data = (page & 0xfffe0000) | asid; /* VALID bit is off */
 
-	if ((cpu_data->flags & CPU_HAS_MMU_PAGE_ASSOC)) {
+	if ((current_cpu_data.flags & CPU_HAS_MMU_PAGE_ASSOC)) {
 		addr |= MMU_PAGE_ASSOC_BIT;
 		ways = 1;	/* we already know the way .. */
 	}