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| author | Valentine Barshak <vbarshak@ru.mvista.com> | 2007-09-22 00:50:09 +1000 |
|---|---|---|
| committer | Josh Boyer <jwboyer@linux.vnet.ibm.com> | 2007-10-03 07:20:18 -0500 |
| commit | 340ffd267c85fc28da7cfd681b177c816af800cf (patch) | |
| tree | b9a757d6d0566420fe103c02d60f2b520e5c3880 /arch/sh64 | |
| parent | 8112753bb2c0045398c89d0647792b39805f6d40 (diff) | |
[POWERPC] 4xx: 440EPx/GRx incorrect write to DDR SDRAM errata workaround
Add a workaround for PowerPC 440EPx/GRx incorrect write to
DDR SDRAM errata. Data can be written to wrong address
in SDRAM when write pipelining enabled on plb0. We disable
it in the cpu_setup for these processors at early init.
Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
Diffstat (limited to 'arch/sh64')
0 files changed, 0 insertions, 0 deletions