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authorPaul Mundt <lethal@linux-sh.org>2009-05-26 23:13:13 +0900
committerPaul Mundt <lethal@linux-sh.org>2009-05-26 23:13:13 +0900
commitb7e2ac619465f1774b827d9997109ceef4a61851 (patch)
tree6cb846c7f6c3b71e9f6ae9560e539e61f724f284 /arch/sh
parentd076d2bd0d9379314df5f2ab8b9c83f617c70923 (diff)
sh: pci: Disable MWI and make pci_dma_burst_advice() a bit more accurate.
None of the SH PCI controllers support MWI, it is always treated as a direct memory write, so simply disable it outright. In the case of the PCI cache line size, consult that for the pci_dma_burst_advice() strategy, and switch over to PCI_DMA_BURST_MULTIPLE, as PPC64. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh')
-rw-r--r--arch/sh/include/asm/pci.h20
1 files changed, 18 insertions, 2 deletions
diff --git a/arch/sh/include/asm/pci.h b/arch/sh/include/asm/pci.h
index 5b2e0fcdfc2..ae0da6f48b6 100644
--- a/arch/sh/include/asm/pci.h
+++ b/arch/sh/include/asm/pci.h
@@ -89,12 +89,28 @@ static inline void pcibios_penalize_isa_irq(int irq, int active)
#endif
#ifdef CONFIG_PCI
+/*
+ * None of the SH PCI controllers support MWI, it is always treated as a
+ * direct memory write.
+ */
+#define PCI_DISABLE_MWI
+
static inline void pci_dma_burst_advice(struct pci_dev *pdev,
enum pci_dma_burst_strategy *strat,
unsigned long *strategy_parameter)
{
- *strat = PCI_DMA_BURST_INFINITY;
- *strategy_parameter = ~0UL;
+ unsigned long cacheline_size;
+ u8 byte;
+
+ pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte);
+
+ if (byte == 0)
+ cacheline_size = L1_CACHE_BYTES;
+ else
+ cacheline_size = byte << 2;
+
+ *strat = PCI_DMA_BURST_MULTIPLE;
+ *strategy_parameter = cacheline_size;
}
#endif