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authorDavid S. Miller <davem@davemloft.net>2006-01-31 18:33:00 -0800
committerDavid S. Miller <davem@sunset.davemloft.net>2006-03-20 01:11:22 -0800
commit4da808c352c290d3f762933d44d4ab90c2fd65f3 (patch)
treeda99326440777580a19c345a5b0d52fbf800042b /arch/sparc64/lib/clear_page.S
parent4753eb2ac7022b999e5e484f1a5dc001dba22bd3 (diff)
[SPARC64]: Fix bogus flush instruction usage.
Some of the trap code was still assuming that alternate global %g6 was hard coded with current_thread_info(). Let's just consistently flush at KERNBASE when we need a pipeline synchronization. That's locked into the TLB and will always work. Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'arch/sparc64/lib/clear_page.S')
-rw-r--r--arch/sparc64/lib/clear_page.S4
1 files changed, 3 insertions, 1 deletions
diff --git a/arch/sparc64/lib/clear_page.S b/arch/sparc64/lib/clear_page.S
index b59884ef051..cdc634bceba 100644
--- a/arch/sparc64/lib/clear_page.S
+++ b/arch/sparc64/lib/clear_page.S
@@ -9,6 +9,7 @@
#include <asm/page.h>
#include <asm/pgtable.h>
#include <asm/spitfire.h>
+#include <asm/head.h>
/* What we used to do was lock a TLB entry into a specific
* TLB slot, clear the page with interrupts disabled, then
@@ -66,7 +67,8 @@ clear_user_page: /* %o0=dest, %o1=vaddr */
wrpr %o4, PSTATE_IE, %pstate
stxa %o0, [%g3] ASI_DMMU
stxa %g1, [%g0] ASI_DTLB_DATA_IN
- flush %g6
+ sethi %hi(KERNBASE), %g1
+ flush %g1
wrpr %o4, 0x0, %pstate
mov 1, %o4