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authorJeremy Fitzhardinge <jeremy.fitzhardinge@citrix.com>2009-04-24 00:26:50 -0700
committerJeremy Fitzhardinge <jeremy.fitzhardinge@citrix.com>2009-05-08 15:55:24 -0700
commita789ed5fb6d0256c4177c2cc27e06520ddbe4d4c (patch)
treeafdbb0c64c15ec522eae260949bfec02df2291b2 /arch/x86/include
parentb80119bb35a49a4e8dbfb9708872adfd5cf38dee (diff)
xen: cache cr0 value to avoid trap'n'emulate for read_cr0
stts() is implemented in terms of read_cr0/write_cr0 to update the state of the TS bit. This happens during context switch, and so is fairly performance critical. Rather than falling back to a trap-and-emulate native read_cr0, implement our own by caching the last-written value from write_cr0 (the TS bit is the only one we really care about). Impact: optimise Xen context switches Signed-off-by: Jeremy Fitzhardinge <jeremy.fitzhardinge@citrix.com>
Diffstat (limited to 'arch/x86/include')
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