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authorPeter Zijlstra <a.p.zijlstra@chello.nl>2009-06-11 14:19:11 +0200
committerIngo Molnar <mingo@elte.hu>2009-06-11 17:54:17 +0200
commit8be6e8f3c3a13900169f1141870562d0c723b010 (patch)
tree0041b2557561ada3566bd309f0b3153e31a9854c /arch/x86/kernel/cpu/perf_counter.c
parentf4dbfa8f3131a84257223393905f7efad0ca5996 (diff)
perf_counter: Rename L2 to LL cache
The top (fastest) and last level (biggest) caches are the most interesting ones, performance wise. Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Mike Galbraith <efault@gmx.de> Cc: Paul Mackerras <paulus@samba.org> Cc: Arnaldo Carvalho de Melo <acme@redhat.com> LKML-Reference: <new-submission> [ Fixed the Nehalem LL table to LLC Reference/Miss events ] Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/x86/kernel/cpu/perf_counter.c')
-rw-r--r--arch/x86/kernel/cpu/perf_counter.c12
1 files changed, 6 insertions, 6 deletions
diff --git a/arch/x86/kernel/cpu/perf_counter.c b/arch/x86/kernel/cpu/perf_counter.c
index 572fb434a66..895c82e7845 100644
--- a/arch/x86/kernel/cpu/perf_counter.c
+++ b/arch/x86/kernel/cpu/perf_counter.c
@@ -131,7 +131,7 @@ static const u64 nehalem_hw_cache_event_ids
[ C(RESULT_MISS) ] = 0x0,
},
},
- [ C(L2 ) ] = {
+ [ C(LL ) ] = {
[ C(OP_READ) ] = {
[ C(RESULT_ACCESS) ] = 0x0324, /* L2_RQSTS.LOADS */
[ C(RESULT_MISS) ] = 0x0224, /* L2_RQSTS.LD_MISS */
@@ -141,8 +141,8 @@ static const u64 nehalem_hw_cache_event_ids
[ C(RESULT_MISS) ] = 0x0824, /* L2_RQSTS.RFO_MISS */
},
[ C(OP_PREFETCH) ] = {
- [ C(RESULT_ACCESS) ] = 0xc024, /* L2_RQSTS.PREFETCHES */
- [ C(RESULT_MISS) ] = 0x8024, /* L2_RQSTS.PREFETCH_MISS */
+ [ C(RESULT_ACCESS) ] = 0x4f2e, /* LLC Reference */
+ [ C(RESULT_MISS) ] = 0x412e, /* LLC Misses */
},
},
[ C(DTLB) ] = {
@@ -222,7 +222,7 @@ static const u64 core2_hw_cache_event_ids
[ C(RESULT_MISS) ] = 0,
},
},
- [ C(L2 ) ] = {
+ [ C(LL ) ] = {
[ C(OP_READ) ] = {
[ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
[ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
@@ -313,7 +313,7 @@ static const u64 atom_hw_cache_event_ids
[ C(RESULT_MISS) ] = 0,
},
},
- [ C(L2 ) ] = {
+ [ C(LL ) ] = {
[ C(OP_READ) ] = {
[ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
[ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
@@ -422,7 +422,7 @@ static const u64 amd_0f_hw_cache_event_ids
[ C(RESULT_MISS) ] = 0,
},
},
- [ C(L2 ) ] = {
+ [ C(LL ) ] = {
[ C(OP_READ) ] = {
[ C(RESULT_ACCESS) ] = 0,
[ C(RESULT_MISS) ] = 0,