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authorThomas Gleixner <tglx@linutronix.de>2008-09-06 03:06:08 +0200
committerThomas Gleixner <tglx@linutronix.de>2008-09-06 07:21:17 +0200
commit72d43d9bc9210d24d09202eaf219eac09e17b339 (patch)
tree0ec1d67060e32ad3e2b3772d0c0cb33a8809b594 /arch/x86/kernel/hpet.c
parentf7676254f179eac6b5244a80195ec8ae0e9d4606 (diff)
x86: HPET: read back compare register before reading counter
After fixing the u32 thinko I sill had occasional hickups on ATI chipsets with small deltas. There seems to be a delay between writing the compare register and the transffer to the internal register which triggers the interrupt. Reading back the value makes sure, that it hit the internal match register befor we compare against the counter value. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'arch/x86/kernel/hpet.c')
-rw-r--r--arch/x86/kernel/hpet.c7
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/x86/kernel/hpet.c b/arch/x86/kernel/hpet.c
index 801497a16e0..73deaffadd0 100644
--- a/arch/x86/kernel/hpet.c
+++ b/arch/x86/kernel/hpet.c
@@ -278,6 +278,13 @@ static int hpet_legacy_next_event(unsigned long delta,
cnt += (u32) delta;
hpet_writel(cnt, HPET_T0_CMP);
+ /*
+ * We need to read back the CMP register to make sure that
+ * what we wrote hit the chip before we compare it to the
+ * counter.
+ */
+ WARN_ON((u32)hpet_readl(HPET_T0_CMP) != cnt);
+
return (s32)((u32)hpet_readl(HPET_COUNTER) - cnt) >= 0 ? -ETIME : 0;
}