aboutsummaryrefslogtreecommitdiff
path: root/arch/x86/kernel
diff options
context:
space:
mode:
authorIngo Molnar <mingo@elte.hu>2009-01-28 05:01:41 +0100
committerIngo Molnar <mingo@elte.hu>2009-01-28 23:20:17 +0100
commitf6f52baf2613dd319e9ba3f3319bf1f1c442e4b3 (patch)
tree1eb8f814939501c10f3f18af86f9c5a5d25c7310 /arch/x86/kernel
parentfe402e1f2b67a63f1e53ab2a316fc20f7ca4ec91 (diff)
x86: clean up esr_disable() methods
Impact: cleanup Most subarchitectures want to disable the APIC ESR (Error Status Register), because they generally have hardware hacks that wrap standard CPUs into a bigger system and hence the APIC bus is quite non-standard and weirdnesses (lockups) have been seen with ESR reporting. Remove the esr_disable macros and put the desired flag into each subarchitecture's genapic template directly. Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/x86/kernel')
-rw-r--r--arch/x86/kernel/apic.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/x86/kernel/apic.c b/arch/x86/kernel/apic.c
index b6740de18fb..69d8c30d571 100644
--- a/arch/x86/kernel/apic.c
+++ b/arch/x86/kernel/apic.c
@@ -1107,7 +1107,7 @@ static void __cpuinit lapic_setup_esr(void)
return;
}
- if (esr_disable) {
+ if (apic->ESR_DISABLE) {
/*
* Something untraceable is creating bad interrupts on
* secondary quads ... for the moment, just leave the
@@ -1157,7 +1157,7 @@ void __cpuinit setup_local_APIC(void)
#ifdef CONFIG_X86_32
/* Pound the ESR really hard over the head with a big hammer - mbligh */
- if (lapic_is_integrated() && esr_disable) {
+ if (lapic_is_integrated() && apic->ESR_DISABLE) {
apic_write(APIC_ESR, 0);
apic_write(APIC_ESR, 0);
apic_write(APIC_ESR, 0);