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authorSuresh Siddha <suresh.b.siddha@intel.com>2008-08-27 14:57:36 -0700
committerH. Peter Anvin <hpa@zytor.com>2008-08-27 15:23:23 -0700
commit83b8e28b14d63db928cb39e5c5ed2a548246bd71 (patch)
tree27abd5df0e150e411265ac5a2c834279813eb8dc /arch/x86/power/cpu_64.c
parentf65bc214e042916135256620f900e9599d65e0cb (diff)
x86: xsave: restore xcr0 during resume
Add the missing XCR0(XFEATURE_ENABLED_MASK) restore during resume. Reported-by: Venkatesh Pallipadi <venkatesh.pallipadi@intel.com> Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com> Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Diffstat (limited to 'arch/x86/power/cpu_64.c')
-rw-r--r--arch/x86/power/cpu_64.c7
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/x86/power/cpu_64.c b/arch/x86/power/cpu_64.c
index 66bdfb591fd..e3b6cf70d62 100644
--- a/arch/x86/power/cpu_64.c
+++ b/arch/x86/power/cpu_64.c
@@ -14,6 +14,7 @@
#include <asm/page.h>
#include <asm/pgtable.h>
#include <asm/mtrr.h>
+#include <asm/xcr.h>
static void fix_processor_context(void);
@@ -122,6 +123,12 @@ static void __restore_processor_state(struct saved_context *ctxt)
wrmsrl(MSR_GS_BASE, ctxt->gs_base);
wrmsrl(MSR_KERNEL_GS_BASE, ctxt->gs_kernel_base);
+ /*
+ * restore XCR0 for xsave capable cpu's.
+ */
+ if (cpu_has_xsave)
+ xsetbv(XCR_XFEATURE_ENABLED_MASK, pcntxt_mask);
+
fix_processor_context();
do_fpu_end();