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authorDaniel Qarras <dqarras@yahoo.com>2009-07-12 04:32:40 -0700
committerIngo Molnar <mingo@elte.hu>2009-07-13 08:46:51 +0200
commitf1c6a58121f9846ac665b0fbd3cbab90ce8bcbac (patch)
treecdc44904341a5669ba37c407bcc3d94e0acf875d /arch/x86
parente3d7e183dc276df2fcaf02af173a49ad119ba9f9 (diff)
perf_counter, x86: Extend perf_counter Pentium M support
I've attached a patch to remove the Pentium M special casing of EMON and as noticed at least with my Pentium M the hardware PMU now works: Performance counter stats for '/bin/ls /var/tmp': 1.809988 task-clock-msecs # 0.125 CPUs 1 context-switches # 0.001 M/sec 0 CPU-migrations # 0.000 M/sec 224 page-faults # 0.124 M/sec 1425648 cycles # 787.656 M/sec 912755 instructions # 0.640 IPC Vince suggested that this code was trying to address erratum Y17 in Pentium-M's: http://download.intel.com/support/processors/mobile/pm/sb/25266532.pdf But that erratum (related to IA32_MISC_ENABLES.7) does not affect perfcounters as we dont use this toggle to disable RDPMC and WRMSR/RDMSR access to performance counters. We keep cr4's bit 8 (X86_CR4_PCE) clear so unprivileged RDPMC access is not allowed anyway. Cc: Vince Weaver <vince@deater.net> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Stephane Eranian <eranian@googlemail.com> LKML-Reference: <new-submission> Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/x86')
-rw-r--r--arch/x86/kernel/cpu/perf_counter.c6
1 files changed, 2 insertions, 4 deletions
diff --git a/arch/x86/kernel/cpu/perf_counter.c b/arch/x86/kernel/cpu/perf_counter.c
index bed1c4c2f25..7e346d4bc0f 100644
--- a/arch/x86/kernel/cpu/perf_counter.c
+++ b/arch/x86/kernel/cpu/perf_counter.c
@@ -1583,10 +1583,8 @@ static int p6_pmu_init(void)
break;
case 9:
case 13:
- /* for Pentium M, we need to check if PMU exist */
- rdmsr(MSR_IA32_MISC_ENABLE, low, high);
- if (low & MSR_IA32_MISC_ENABLE_EMON)
- break;
+ /* Pentium M */
+ break;
default:
pr_cont("unsupported p6 CPU model %d ",
boot_cpu_data.x86_model);