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authorAndi Kleen <ak@suse.de>2006-07-29 21:42:37 +0200
committerLinus Torvalds <torvalds@g5.osdl.org>2006-07-29 20:59:55 -0700
commit0e5f61b00c577da698fb00cd9c91a96b79044dfd (patch)
treede9e4c79ff38247988859e41350212b41fe882df /arch/x86_64
parent260f659b232b17889e3f0c9bf411675898b222c2 (diff)
[PATCH] x86_64: On Intel systems when CPU has C3 don't use TSC
On Intel systems generally the TSC stops in C3 or deeper, so don't use it there. Follows similar logic on i386. This should fix problems on Meroms. Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'arch/x86_64')
-rw-r--r--arch/x86_64/kernel/time.c16
1 files changed, 12 insertions, 4 deletions
diff --git a/arch/x86_64/kernel/time.c b/arch/x86_64/kernel/time.c
index e0341c6808e..7a9b1822418 100644
--- a/arch/x86_64/kernel/time.c
+++ b/arch/x86_64/kernel/time.c
@@ -28,6 +28,7 @@
#include <linux/acpi.h>
#ifdef CONFIG_ACPI
#include <acpi/achware.h> /* for PM timer frequency */
+#include <acpi/acpi_bus.h>
#endif
#include <asm/8253pit.h>
#include <asm/pgtable.h>
@@ -953,11 +954,18 @@ __cpuinit int unsynchronized_tsc(void)
#ifdef CONFIG_SMP
if (apic_is_clustered_box())
return 1;
- /* Intel systems are normally all synchronized. Exceptions
- are handled in the check above. */
- if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
- return 0;
#endif
+ /* Most intel systems have synchronized TSCs except for
+ multi node systems */
+ if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) {
+#ifdef CONFIG_ACPI
+ /* But TSC doesn't tick in C3 so don't use it there */
+ if (acpi_fadt.length > 0 && acpi_fadt.plvl3_lat < 100)
+ return 1;
+#endif
+ return 0;
+ }
+
/* Assume multi socket systems are not synchronized */
return num_present_cpus() > 1;
}