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authorMatt Porter <mporter@kernel.crashing.org>2005-09-03 15:55:42 -0700
committerLinus Torvalds <torvalds@evo.osdl.org>2005-09-05 00:05:57 -0700
commit656de7e46901fe3228b592e1d9fc89c353f0fa4e (patch)
treee2d354af516f02e381558f9d525b16456425fe6a /arch
parentac6295c289f205bed59b1edfdc4518468db7b1cb (diff)
[PATCH] ppc32: add cputable entry for 440SP Rev. A
Adds the appropriate cputable entry for PPC440SP so cache line sizes are configured correctly. Signed-off-by: Matt Porter <mporter@kernel.crashing.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/ppc/kernel/cputable.c10
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/ppc/kernel/cputable.c b/arch/ppc/kernel/cputable.c
index 22c187c1f53..61382341bb0 100644
--- a/arch/ppc/kernel/cputable.c
+++ b/arch/ppc/kernel/cputable.c
@@ -932,6 +932,16 @@ struct cpu_spec cpu_specs[] = {
.icache_bsize = 32,
.dcache_bsize = 32,
},
+ { /* 440SP Rev. A */
+ .pvr_mask = 0xff000fff,
+ .pvr_value = 0x53000891,
+ .cpu_name = "440SP Rev. A",
+ .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
+ CPU_FTR_USE_TB,
+ .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
+ .icache_bsize = 32,
+ .dcache_bsize = 32,
+ },
#endif /* CONFIG_44x */
#ifdef CONFIG_FSL_BOOKE
{ /* e200z5 */