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authorImre Deak <imre.deak@nokia.com>2006-06-26 16:16:07 -0700
committerTony Lindgren <tony@atomide.com>2006-06-26 16:16:07 -0700
commit99c477074de4a91a388aff863646dc3e2eb783e2 (patch)
treed3cd4f913d4c7a2113167a6007fd33397335dac6 /arch
parenteca9e56eb8dfcf2b8b966c1c49e4622196f0586d (diff)
ARM: OMAP: Fix GPIO IRQ mask handling
The GPIO IRQ mask was retrieved incorrectly in cases where we have a mask register instead of an enable register. Also we should only return the valid bits depending on the bank size. This fixes a bug on 1510/1610 based OMAPs where GPIO IRQs are not delivered. Signed-off-by: Imre Deak <imre.deak@nokia.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/plat-omap/gpio.c17
1 files changed, 16 insertions, 1 deletions
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index cd1e508f90c..e75a2ca70ba 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -540,29 +540,44 @@ static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
{
void __iomem *reg = bank->base;
+ int inv = 0;
+ u32 l;
+ u32 mask;
switch (bank->method) {
case METHOD_MPUIO:
reg += OMAP_MPUIO_GPIO_MASKIT;
+ mask = 0xffff;
+ inv = 1;
break;
case METHOD_GPIO_1510:
reg += OMAP1510_GPIO_INT_MASK;
+ mask = 0xffff;
+ inv = 1;
break;
case METHOD_GPIO_1610:
reg += OMAP1610_GPIO_IRQENABLE1;
+ mask = 0xffff;
break;
case METHOD_GPIO_730:
reg += OMAP730_GPIO_INT_MASK;
+ mask = 0xffffffff;
+ inv = 1;
break;
case METHOD_GPIO_24XX:
reg += OMAP24XX_GPIO_IRQENABLE1;
+ mask = 0xffffffff;
break;
default:
BUG();
return 0;
}
- return __raw_readl(reg);
+ l = __raw_readl(reg);
+ if (inv)
+ l = ~l;
+ l &= mask;
+ return l;
}
static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)