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authorVojtech Pavlik <vojtech@suse.cz>2006-06-26 13:58:35 +0200
committerLinus Torvalds <torvalds@g5.osdl.org>2006-06-26 10:48:19 -0700
commitb2df3ddb68fc02e3bae78b7adaeca8561d02ea6d (patch)
tree6787e6674fc52b1b31032cfa3edcf40034bf6bf0 /arch
parent4221133845f81ab4428c79a89e37be2c87624c1a (diff)
[PATCH] x86_64: Explain why HPET T0_CMP register is written twice
After writing the CFG register, the first value written to the T0_CMP register is the value at which next interrupt should be triggered, every value after that sets the period of the interrupt. For that reason, the code needs to write the value twice - to set both the phase and period. [AK: I had already figured it out by myself, but it's still useful to have a comment for this.] Signed-off-by: Vojtech Pavlik <vojtech@suse.cz> Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/x86_64/kernel/time.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/x86_64/kernel/time.c b/arch/x86_64/kernel/time.c
index 51afb07bc14..ee622ac0376 100644
--- a/arch/x86_64/kernel/time.c
+++ b/arch/x86_64/kernel/time.c
@@ -795,8 +795,8 @@ static int hpet_timer_stop_set_go(unsigned long tick)
if (hpet_use_timer) {
hpet_writel(HPET_TN_ENABLE | HPET_TN_PERIODIC | HPET_TN_SETVAL |
HPET_TN_32BIT, HPET_T0_CFG);
- hpet_writel(hpet_tick, HPET_T0_CMP);
- hpet_writel(hpet_tick, HPET_T0_CMP); /* AK: why twice? */
+ hpet_writel(hpet_tick, HPET_T0_CMP); /* next interrupt */
+ hpet_writel(hpet_tick, HPET_T0_CMP); /* period */
cfg |= HPET_CFG_LEGACY;
}
/*