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authorValentine Barshak <vbarshak@ru.mvista.com>2007-12-22 04:22:39 +1100
committerJosh Boyer <jwboyer@linux.vnet.ibm.com>2007-12-23 13:36:07 -0600
commit0b2e97518da185b87144992e1f0bdacd904dcbb9 (patch)
tree76e89c1877d78ae47fef238365bedd1de0925a15 /arch
parent14b3d926a22b89f779229f88ed16a76b6b641b1c (diff)
[POWERPC] 4xx: Add PCI entry to 440GRx Rainier DTS.
This adds PCI entry to PowerPC 440GRx Rainier DTS. Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/powerpc/boot/dts/rainier.dts27
1 files changed, 27 insertions, 0 deletions
diff --git a/arch/powerpc/boot/dts/rainier.dts b/arch/powerpc/boot/dts/rainier.dts
index 63d996e647c..d0e9e16aba6 100644
--- a/arch/powerpc/boot/dts/rainier.dts
+++ b/arch/powerpc/boot/dts/rainier.dts
@@ -308,6 +308,33 @@
has-new-stacr-staopc;
};
};
+
+ PCI0: pci@1ec000000 {
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ compatible = "ibm,plb440grx-pci", "ibm,plb-pci";
+ primary;
+ reg = <1 eec00000 8 /* Config space access */
+ 1 eed00000 4 /* IACK */
+ 1 eed00000 4 /* Special cycle */
+ 1 ef400000 40>; /* Internal registers */
+
+ /* Outbound ranges, one memory and one IO,
+ * later cannot be changed. Chip supports a second
+ * IO range but we don't use it for now
+ */
+ ranges = <02000000 0 80000000 1 80000000 0 10000000
+ 01000000 0 00000000 1 e8000000 0 00100000>;
+
+ /* Inbound 2GB range starting at 0 */
+ dma-ranges = <42000000 0 0 0 0 0 80000000>;
+
+ /* All PCI interrupts are routed to IRQ 67 */
+ interrupt-map-mask = <0000 0 0 0>;
+ interrupt-map = < 0000 0 0 0 &UIC2 3 8 >;
+ };
};
chosen {