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author | Paul Walmsley <paul@pwsan.com> | 2009-01-28 12:27:42 -0700 |
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committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2009-02-08 17:50:40 +0000 |
commit | 0eafd4725cf5d828e76e474b8991a228bbdd3f2b (patch) | |
tree | 797186618cb16d1ddb3f42a1ac9c9d4f84bdc7c1 /block/cfq-iosched.c | |
parent | 87246b7567f7d1951bfcea29875523ef435c0ebf (diff) |
[ARM] OMAP3 clock: add omap3_core_dpll_m2_set_rate()
Add the omap3_core_dpll_m2_set_rate() function to the OMAP3 clock code,
which calls into the SRAM function omap3_sram_configure_core_dpll() to
change the CORE DPLL M2 divider. (SRAM code is necessary since rate changes
on clocks upstream from the SDRC can glitch SDRAM accesses.)
Use this function for the set_rate function pointer in the dpll3_m2_ck
struct clk. With this function in place, PM/OPP code should be able to
alter SDRAM speed via code similar to:
clk_set_rate(&dpll3_m2_ck, target_rate).
linux-omap source commit is 7f8b2b0f4fe52238c67d79dedcd2794dcef4dddd.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'block/cfq-iosched.c')
0 files changed, 0 insertions, 0 deletions