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authorJack Steiner <steiner@sgi.com>2009-09-03 12:56:02 -0500
committerH. Peter Anvin <hpa@zytor.com>2009-09-09 14:05:24 -0700
commitfa526d0d641b5365676a1fb821ce359e217c9b85 (patch)
treefa08cded30f46df90fe103a750f412e306f2d53e /crypto/async_tx
parenta269cca9926faf8e44b340b017be0d884203141b (diff)
x86, pat: Fix cacheflush address in change_page_attr_set_clr()
Fix address passed to cpa_flush_range() when changing page attributes from WB to UC. The address (*addr) is modified by __change_page_attr_set_clr(). The result is that the pages being flushed start at the _end_ of the changed range instead of the beginning. This should be considered for 2.6.30-stable and 2.6.31-stable. Signed-off-by: Jack Steiner <steiner@sgi.com> Acked-by: Suresh Siddha <suresh.b.siddha@intel.com> Signed-off-by: H. Peter Anvin <hpa@zytor.com> Cc: Stable team <stable@kernel.org>
Diffstat (limited to 'crypto/async_tx')
0 files changed, 0 insertions, 0 deletions