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authorLennert Buytenhek <buytenh@wantstofly.org>2009-02-20 02:32:30 +0100
committerNicolas Pitre <nico@cam.org>2009-02-19 22:43:14 -0500
commitf1f5465782a96201798ef1e8167ed3ffaefdb30d (patch)
tree8fa52172861ee9e6c5f6b74335bac723938851b1 /drivers/base
parent712424fd95134bf88d27f3885389fe6ab13f34ac (diff)
[ARM] mv78xx0: enable eth2/eth3 on the mv78xx0 A0 development board
The A0 revision of the mv78xx0 development board has four ethernet ports, with PHY IDs 8-11, whereas the Z0 version has two, with PHY addresses 8-9. This patch configures the third and fourth ethernet port to use the PHY addresses on the A0 board to enable use of those ports -- if we are running on a Z0 board, the ge10/11 setup code in common.c will force these back to PHYless mode. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
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