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authorDan Williams <dan.j.williams@intel.com>2007-07-20 02:07:26 +0100
committerRussell King <rmk+kernel@arm.linux.org.uk>2007-07-20 09:35:42 +0100
commit70c14ff0e9f5e1f5456587b827620e636ba70a09 (patch)
treebcd34365e64d6537d833f649a46a534f3a0ff2c6 /drivers/char/watchdog/Kconfig
parent7dea1b20066cd30fb54da7e686b16b5e38b46b2d (diff)
[ARM] 4495/1: iop: combined watchdog timer driver for iop3xx and iop13xx
In order for this driver to be shared across the iop architectures the iop3xx and iop13xx header files are modified to present a common interface for the iop_wdt driver. Details: * iop13xx supports disabling the timer while iop3xx does not. This requires a few 'compatibility' definitions in include/asm-arm/hardware/iop3xx.h to preclude adding #ifdef CONFIG_ARCH_IOP13XX blocks to the driver code. * The heartbeat interval is derived from the internal bus clock rate, so this this patch also exports the tick rate to the iop_wdt driver. Cc: Curt Bruns <curt.e.bruns@intel.com> Cc: Peter Milne <peter.milne@d-tacq.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com> Acked-by: Wim Van Sebroeck <wim@iguana.be> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'drivers/char/watchdog/Kconfig')
-rw-r--r--drivers/char/watchdog/Kconfig16
1 files changed, 16 insertions, 0 deletions
diff --git a/drivers/char/watchdog/Kconfig b/drivers/char/watchdog/Kconfig
index 2f48ba32996..a4d81cda479 100644
--- a/drivers/char/watchdog/Kconfig
+++ b/drivers/char/watchdog/Kconfig
@@ -187,6 +187,22 @@ config PNX4008_WATCHDOG
Say N if you are unsure.
+config IOP_WATCHDOG
+ tristate "IOP Watchdog"
+ depends on WATCHDOG && PLAT_IOP
+ select WATCHDOG_NOWAYOUT if (ARCH_IOP32X || ARCH_IOP33X)
+ help
+ Say Y here if to include support for the watchdog timer
+ in the Intel IOP3XX & IOP13XX I/O Processors. This driver can
+ be built as a module by choosing M. The module will
+ be called iop_wdt.
+
+ Note: The IOP13XX watchdog does an Internal Bus Reset which will
+ affect both cores and the peripherals of the IOP. The ATU-X
+ and/or ATUe configuration registers will remain intact, but if
+ operating as an Root Complex and/or Central Resource, the PCI-X
+ and/or PCIe busses will also be reset. THIS IS A VERY BIG HAMMER.
+
# AVR32 Architecture
config AT32AP700X_WDT