diff options
| author | Jesse Barnes <jbarnes@virtuousgeek.org> | 2008-11-12 10:03:55 -0800 |
|---|---|---|
| committer | Dave Airlie <airlied@linux.ie> | 2008-12-29 17:47:23 +1000 |
| commit | de151cf67ce52ed2d88083daa5e60c7858947329 (patch) | |
| tree | 860c46d95061b261a7cab24a6ab57b68a0146f3a /drivers/gpu/drm/i915/i915_reg.h | |
| parent | a2c0a97b784f837300f7b0869c82ab712c600952 (diff) | |
drm/i915: add GEM GTT mapping support
Use the new core GEM object mapping code to allow GTT mapping of GEM
objects on i915. The fault handler will make sure a fence register is
allocated too, if the object in question is tiled.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 20 |
1 files changed, 19 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 9d24aaeb8a4..47e6bafeb74 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -175,9 +175,26 @@ #define DISPLAY_PLANE_B (1<<20) /* - * Instruction and interrupt control regs + * Fence registers */ +#define FENCE_REG_830_0 0x2000 +#define I830_FENCE_START_MASK 0x07f80000 +#define I830_FENCE_TILING_Y_SHIFT 12 +#define I830_FENCE_SIZE_BITS(size) ((get_order(size >> 19) - 1) << 8) +#define I830_FENCE_PITCH_SHIFT 4 +#define I830_FENCE_REG_VALID (1<<0) + +#define I915_FENCE_START_MASK 0x0ff00000 +#define I915_FENCE_SIZE_BITS(size) ((get_order(size >> 20) - 1) << 8) +#define FENCE_REG_965_0 0x03000 +#define I965_FENCE_PITCH_SHIFT 2 +#define I965_FENCE_TILING_Y_SHIFT 1 +#define I965_FENCE_REG_VALID (1<<0) + +/* + * Instruction and interrupt control regs + */ #define PRB0_TAIL 0x02030 #define PRB0_HEAD 0x02034 #define PRB0_START 0x02038 @@ -245,6 +262,7 @@ #define CM0_RC_OP_FLUSH_DISABLE (1<<0) #define GFX_FLSH_CNTL 0x02170 /* 915+ only */ + /* * Framebuffer compression (915+ only) */ |