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authorAlex Deucher <alexdeucher@gmail.com>2010-03-31 00:33:27 -0400
committerDave Airlie <airlied@redhat.com>2010-03-31 14:54:47 +1000
commitf46c01208da1881591e3f55ca77d37f54469f8e4 (patch)
tree39b9169c70da504b80440b85b5ef2ffa4394d25f /drivers/gpu/drm/radeon/r100.c
parent3b01a1191fe76bd11e5743eceed7c25d8157239e (diff)
drm/radeon/kms: display watermark updates (v2)
- Add module option to force the display priority 0 = auto, 1 = normal, 2 = high - Default to high on r3xx/r4xx/rv515 chips Fixes flickering problems during heavy acceleration due to underflow to the display controllers - Fill in minimal support for RS600 v2 - update display priority when bandwidth is updated so the user can change the parameter at runtime and it will take affect on the next modeset. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/r100.c')
-rw-r--r--drivers/gpu/drm/radeon/r100.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index 739a44783ef..138ddd49dfc 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -2389,6 +2389,8 @@ void r100_bandwidth_update(struct radeon_device *rdev)
uint32_t pixel_bytes1 = 0;
uint32_t pixel_bytes2 = 0;
+ radeon_update_display_priority(rdev);
+
if (rdev->mode_info.crtcs[0]->base.enabled) {
mode1 = &rdev->mode_info.crtcs[0]->base.mode;
pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;