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authorJesse Barnes <jbarnes@virtuousgeek.org>2009-07-16 13:01:01 -0700
committerEric Anholt <eric@anholt.net>2009-07-16 13:02:33 -0700
commit390c4dd448b1a5f04ea497c20f5ff664f8eeed01 (patch)
treea9a35b483382b65673843c661e058b8561e5f911 /drivers/gpu/drm
parentdff33cfcefa31c30b72c57f44586754ea9e8f3e2 (diff)
drm/i915: handle FIFO oversubsription correctly
If you're pushing a plane hard (i.e. you need most or all of the FIFO entries just to cover your frame refresh latency), the watermark level may end up being negative. So fix up the signed vs. unsigned math in the calculation function to handle this correctly, giving all available FIFO entries to such a configuration. Reported-by: Eric Anholt <eric@anholt.net> Tested-by: Eric Anholt <eric@anholt.net> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
Diffstat (limited to 'drivers/gpu/drm')
-rw-r--r--drivers/gpu/drm/i915/intel_display.c7
1 files changed, 4 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 3fa0d63c83b..890f7108e72 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1674,7 +1674,7 @@ static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
int pixel_size,
unsigned long latency_ns)
{
- unsigned long entries_required, wm_size;
+ long entries_required, wm_size;
entries_required = (clock_in_khz * pixel_size * latency_ns) / 1000000;
entries_required /= wm->cacheline_size;
@@ -1685,9 +1685,10 @@ static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
DRM_DEBUG("FIFO watermark level: %d\n", wm_size);
- if (wm_size > wm->max_wm)
+ /* Don't promote wm_size to unsigned... */
+ if (wm_size > (long)wm->max_wm)
wm_size = wm->max_wm;
- if (wm_size == 0)
+ if (wm_size <= 0)
wm_size = wm->default_wm;
return wm_size;
}